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參數(shù)資料
| 型號(hào)： | MC68HC08LT8 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 英文描述： | Microcontrollers |
| 中文描述： | 微控制器 |
| 文件頁(yè)數(shù)： | 118/156頁(yè) |
| 文件大?。?/td> | 1030K |
| 代理商： | MC68HC08LT8 |
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Computer Operating Properly (COP)
MC68HC08LT8 Data Sheet, Rev. 1
118
Freescale Semiconductor
The COP counter is a free-running 6-bit counter preceded by the 12-bit system integration module (SIM)
counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after
2
18
– 2
4
or 2
13
– 2
4
CGMXCLK cycles; depending on the state of the COP rate select bit, COPRS, in
CONFIG1 register. Writing any value to location $FFFF before an overflow occurs prevents a COP reset
by clearing the COP counter and stages 12 through 5 of the SIM counter.
NOTE
Service the COP immediately after reset and before entering or after exiting
stop mode to guarantee the maximum time before the first COP counter
overflow.
A COP reset pulls the RST pin low for 32
×
CGMXCLK cycles and sets the COP bit in the reset status
register (RSR). (See
4.7.2 Reset Status Register (RSR)
.).
NOTE
Place COP clearing instructions in the main program and not in an interrupt
subroutine. Such an interrupt subroutine could keep the COP from
generating a reset even while the main program is not working properly.
12.3 I/O Signals
The following paragraphs describe the signals shown in
Figure 12-1
.
12.3.1 CMGXCLK
CGMXCLK is the crystal oscillator output signal. CGMXCLK frequency is equal to the crystal frequency.
12.3.2 COPCTL Write
Writing any value to the COP control register (COPCTL) (see
12.4 COP Control Register
) clears the COP
counter and clears bits 12 through 5 of the SIM counter. Reading the COP control register returns the low
byte of the reset vector.
12.3.3 Power-On Reset
The power-on reset (POR) circuit in the SIM clears the SIM counter 4096
×
CGMXCLK cycles after
power-up.
12.3.4 Internal Reset
An internal reset clears the SIM counter and the COP counter.
12.3.5 Reset Vector Fetch
A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears
the SIM counter.
12.3.6 COPD (COP Disable)
The COPD signal reflects the state of the COP disable bit (COPD) in the CONFIG1 register.
(See
3.3 Configuration Register 1 (CONFIG1)
.)
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