參數(shù)資料
型號： MC68HC08LT8
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述： Microcontrollers
中文描述： 微控制器
文件頁數(shù)： 135/156頁
文件大?。?/td> 1030K
代理商： MC68HC08LT8
Opcode Map
MC68HC08LT8 Data Sheet, Rev. 1
Freescale Semiconductor
135
14.8 Opcode Map
See
Table 14-2
.
SWI
Software Interrupt
PC
←
(PC) + 1; Push (PCL)
SP
←
(SP) – 1; Push (PCH)
SP
←
(SP) – 1; Push (X)
SP
←
(SP) – 1; Push (A)
SP
←
(SP) – 1; Push (CCR)
SP
←
(SP) – 1; I
←
1
PCH
←
Interrupt Vector High Byte
PCL
←
Interrupt Vector Low Byte
CCR
←
(A)
X
←
(A)
A
←
(CCR)
– – 1 – – – INH
83
9
TAP
TAX
TPA
TST
opr
TSTA
TSTX
TST
opr
,X
TST ,X
TST
opr
,SP
TSX
TXA
TXS
Transfer A to CCR
Transfer A to X
Transfer CCR to A
INH
84
97
85
3D
4D
5D
6D
7D
9E6D
95
9F
94
2
1
1
3
1
1
3
2
4
2
1
2
– – – – – – INH
– – – – – – INH
Test for Negative or Zero
(A) – $00 or (X) – $00 or (M) – $00
0 – –
–
DIR
INH
INH
IX1
IX
SP1
dd
ff
ff
Transfer SP to H:X
Transfer X to A
Transfer H:X to SP
H:X
←
(SP) + 1
A
←
(X)
(SP)
←
(H:X) – 1
I bit
←
0; Inhibit CPU clocking
until interrupted
– – – – – – INH
– – – – – – INH
– – – – – – INH
WAIT
Enable Interrupts; Wait for Interrupt
– – 0 – – – INH
8F
1
A
C
CCR
dd
dd rr
DD
DIR
DIX+
ee ff
EXT
ff
H
H
hh ll
I
ii
IMD
IMM
INH
IX
IX+
IX+D
IX1
IX1+
IX2
M
N
Accumulator
Carry/borrow bit
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct to direct addressing mode
Direct addressing mode
Direct to indexed with post increment addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry bit
Index register high byte
High and low bytes of operand address in extended addressing
Interrupt mask
Immediate operand byte
Immediate source to direct destination addressing mode
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, no offset, post increment addressing mode
Indexed with post increment to direct addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 8-bit offset, post increment addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Negative bit
n
opr
PC
PCH Program counter high byte
PCL Program counter low byte
REL Relative addressing mode
rel
Relative program counter offset byte
rr
Relative program counter offset byte
SP1 Stack pointer, 8-bit offset addressing mode
SP2 Stack pointer 16-bit offset addressing mode
SP
Stack pointer
U
Undefined
V
Overflow bit
X
Index register low byte
Z
Zero bit
&
Logical AND
|
Logical OR
⊕
Logical EXCLUSIVE OR
( )
Contents of
–( )
Negation (two’s complement)
#
Immediate value
Sign extend
←
Loaded with
If
:
Concatenated with
Set or cleared
—
Not affected
Any bit
Operand (one or two bytes)
Program counter
Table 14-1. Instruction Set Summary (Sheet 6 of 6)
Source
Form
Operation
Description
Effect
on CCR
A
M
O
O
C
V H I N Z C
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