參數(shù)資料
型號: MC68HC05V7CFNR2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC68
封裝: PLASTIC, LCC-68
文件頁數(shù): 38/170頁
文件大?。?/td> 589K
代理商: MC68HC05V7CFNR2
MOTOROLA
SECTION 15: MESSAGE DATA LINK CONTROLLER
Page 118
MC68HC05V7 Specification Rev. 1.0
In VPW bit encoding, the tolerances for the both passive and active data bits and symbols
are defined with no gaps between definitions. For example, the maximum length of a
passive logic zero is equal to the minimum length of a passive logic one, and the maximum
length of an active logic zero is equal to the minimum length of a valid SOF symbol
15.5.4.1
Invalid Passive Bit
If the passive to active transition beginning the next data bit or symbol occurs between the
active to passive transition beginning the current data bit or symbol and
a, the current bit
would be invalid. See Figure 15-12(1).
15.5.4.2
Valid Passive Logic Zero
If the passive to active transition beginning the next data bit or symbol occurs between
a
and
b, the current bit would be considered a logic zero. See Figure 15-12(2).
15.5.4.3
Valid Passive Logic One
If the passive to active transition beginning the next data bit or symbol occurs between
b
and
c, the current bit would be considered a logic one. See Figure 15-12(3).
15.5.4.4
Valid EOD Symbol
If the passive to active transition beginning the next data bit or symbol occurs between
c
and
d, the current symbol would be considered a valid EOD symbol. See Figure 15-12(4).
a
bc
b
a
(1) Invalid Passive
(2) Valid Passive
(3) Valid Passive
64
s
128
s
Figure 15-12 :
J1850 VPW Passive Symbols
cd
(4) Valid EOD
Symbol
Logic One
Bit
Logic Zero
200
s
Active
Passive
Active
Passive
Active
Passive
Active
Passive
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