參數(shù)資料
型號: MC68HC05V7CFNR2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC68
封裝: PLASTIC, LCC-68
文件頁數(shù): 122/170頁
文件大?。?/td> 589K
代理商: MC68HC05V7CFNR2
SECTION 6: RESETS
MOTOROLA
Page 41
MC68HC05V7 Specification Rev. 1.0
Figure 6-2:
RESET and POR Timing Diagram
PCH
PCL
OSC1
2
RESET
INTERNAL
PROCESSOR
INTERNAL
ADDRESS
BUS
1
3FFE
3FFF
V
DD
4064
t
cyc
t cyc
t RL
INTERNAL
DATA
BUS
1
3FFE
NEW
PC
3FFF
NOTES:
1.
Internal
timing
signal
and
bus
information
not
available
externally.
2.
OSC1
line
is
not
meant
to
represent
frequency.
It
is
only
used
to
represent
time.
3.
The
next
rising
edge
of
the
internal
processor
clock
following
the
rising
edge
of
RESET
initiates
the
reset
sequence.
4.
V
DD
must
fall
to
a
level
lower
than
V
POR
in
order
to
recognized
as
a
power
on
reset.
3
NEW
OP
CODE
PCL
PCH
NEW
PC
NEW
PC
OP
CODE
NEW
PC
CLOCK
1
0v
<
V
POR
4
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