參數(shù)資料
型號: MC68HC05V7CFNR2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC68
封裝: PLASTIC, LCC-68
文件頁數(shù): 110/170頁
文件大?。?/td> 589K
代理商: MC68HC05V7CFNR2
MOTOROLA
SECTION 5: INTERRUPTS
Page 30
MC68HC05V7 Specification Rev. 1.0
The M68HC05 CPU does not support interruptible instructions, therefore, the maximum
latency to the first instruction of the interrupt service routine must include the longest
instruction execution time plus stacking overhead.
Latency = (Longest instruction execution time + 10) x tCYC secs
An RTI instruction is used to signify when the interrupt software service routine is
completed. The RTI instruction causes the register contents to be recovered from the stack
and normal processing to resume at the next instruction that was to be executed when the
interrupt took place. Figure 5-1 shows the sequence of events that occur during interrupt
processing.
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