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參數(shù)資料
| 型號(hào)： | MC68HC05V7CFNR2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁(yè)數(shù)： | 21/170頁(yè) |
| 文件大?。?/td> | 589K |
| 代理商： | MC68HC05V7CFNR2 |
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SECTION 15: MESSAGE DATA LINK CONTROLLER
MOTOROLA
Page 103
MC68HC05V7 Specification Rev. 1.0
15.3
MDLC Rx/Tx BUFFERS
The Rx and Tx Buffers provide the interface between the CPU Interface and the Protocol
Handler. They provide buffering of data being sent and received, reducing the frequency of
interrupts to the CPU. Please refer to the MCU memory map for details on the starting and
ending addresses of these buffers within the overall memory map.
15.3.1
OUTLINE
During all modes of MCU operation, the Rx and Tx Buffers are mapped as registers.
Memory mapping these buffers requires the MDLC to supply the user with a count of the
number of bytes in each received message and allows the user to tell the MDLC the length
of a message to be transmitted.
Access arbitration is simplified by the following rules:
The user must not read the Rx Buffer until the MDLC signals that an entire
message has been received (Receive Message Successful bit (RXMS) in
the MDLC Status Register (MSR) is set).
The user returns the Rx Buffer resource to the MDLC by writing any value
to the MDLC Receive Status Register (MRSR).
The user must not write to the Tx Buffer after the MDLC has been told to
transmit the message (length of message has been written to the MDLC
Transmit Control Register (MTCR)).
The user must wait until the MDLC has sent the message (indicated by a
CPU interrupt request and the Transmit Message Successful (TXMS) bit
being set), or the message has been aborted (Transmit Abort bit (TXAB)
in the MDLC Control Register (MCR) is toggled) before reloading the Tx
Buffer.
Physical Interface
To CPU
Protocol Handler
MUX Interface
CPU Interface
Rx/Tx
Buffers
To J1850 Bus
MDLC
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