參數(shù)資料
型號: MC68HC05P1AP
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28
封裝: PLASTIC, DIP-28
文件頁數(shù): 95/124頁
文件大?。?/td> 3724K
代理商: MC68HC05P1AP
NON-DISCLOSURE
AGREEMENT
REQUIRED
16-Bit Timer
General Release Specification
MC68HC05P1A Rev. 3.0
16-Bit Timer
registers always contain the free-running counter value that corresponds
to the most recent input capture.
After a read of the MSB of the input capture register pair (ICRH), counter
transfers are inhibited until the LSB of the register pair (ICRL) is also
read. This characteristic forces the minimum pulse period attainable to
be determined by the time required to execute an input capture software
routine in an application.
Reading the LSB of the input capture register pair (ICRL) does not inhibit
transfer of the free-running counter. Again, minimum pulse periods are
ones which allow software to read the LSB of the register pair (ICRL) and
perform needed operations. There is no conflict between reading the
LSB (ICRL) and the free-running counter transfer, since they occur on
opposite edges of the PH2 clock.
Figure 8-10. State Timing Diagram for Input Capture
INPUT
CAPTURE
FLAG
INPUT
CAPTURE
REGISTER
16-BIT FREE-
RUNNING
COUNTER
TCAP
PIN
INPUT
CAPTURE
LATCH
PH2
CLOCK
NOTE: Although the input capture pin is sampled at the rate of PH2, the internal function is updated at the rate of PH4.
$FFEC
$FFED
$FFEE
$FFEF
$FFEB
(SEE NOTE)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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