- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45222 > MC68HC05P1AP (FREESCALE SEMICONDUCTOR INC) 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28 PDF資料下載
參數(shù)資料
| 型號： | MC68HC05P1AP |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁數(shù)： | 66/124頁 |
| 文件大?。?/td> | 3724K |
| 代理商： | MC68HC05P1AP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁當(dāng)前第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁
NON-DISCLOSURE
AGREEMENT
REQUIRED
Resets
General Release Specification
MC68HC05P1A — Rev. 3.0
Resets
5.3 External Reset (RESET)
The reset input is the only external reset and is connected to an internal
Schmitt trigger. The external reset occurs whenever the reset input is
driven below the lower threshold and remains in reset until the RESET
pin rises above the upper threshold. The upper and lower thresholds are
given in Section 10. Electrical Specifications.
5.4 Internal Resets
The two internally generated resets are the initial power-on reset (POR)
function and the COP watchdog timer function.
5.4.1 Power-On Reset (POR)
The internal POR is generated at power-up to allow the clock oscillator
to stabilize. The POR is strictly for power turn-on conditions and should
not be used to detect a drop in the power supply voltage. There is a 4064
PH2 clock cycle oscillator stabilization delay after the oscillator becomes
active.
5.4.2 Computer Operating Properly (COP) Reset
When the COP watchdog timer is enabled (by mask option), the internal
COP reset is generated automatically by a timeout of the COP watchdog
timer. This timer is implemented with an 18-stage ripple counter that
provides a timeout period of 65.5 ms when a 4-MHz oscillator is used.
The COP watchdog counter is cleared by writing a logic 0 to bit zero at
location $1FF0.
The COP watchdog timer can be disabled by mask option or by applying
2
× V
DD to the IRQ pin. When the IRQ pin is returned to its normal
operating voltage range (between VSS and VDD), the COP watchdog
timer output will be restored if the COP mask option is enabled.
The COP register is shared with the most significant bit (MSB) of an
unimplemented user interrupt vector as shown in Figure 5-2. Reading
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68HCL05P1ADW | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| MC68HC05P2CFN | 8-BIT, MROM, MICROCONTROLLER, PQCC32 |
| MC68HC05P2FN | 8-BIT, MROM, MICROCONTROLLER, PQCC32 |
| MC68HC05P3DWR3 | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| MC68HC705P3CS | 8-BIT, OTPROM, MICROCONTROLLER, CDIP28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC05P1CDW | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS Microcontroller Unit |
| MC68HC05P1CP | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS Microcontroller Unit |
| MC68HC05P1DW | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS Microcontroller Unit |
| MC68HC05P1P | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS Microcontroller Unit |
| MC68HC05P3 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:microcomputer unit with 16-bit programmable timer |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。