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參數(shù)資料
| 型號(hào)： | MC68HC05P1AP |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁數(shù)： | 73/124頁 |
| 文件大?。?/td> | 3724K |
| 代理商： | MC68HC05P1AP |
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NON-DISCLOSURE
AGREEMENT
REQUIRED
Operating Modes
General Release Specification
MC68HC05P1A — Rev. 3.0
Operating Modes
This varied delay time is the result of the halt mode exit circuitry testing
the oscillator stabilization delay timer (a feature of stop mode), which has
been free-running (a feature of wait mode).
NOTE:
Halt mode is not intended for normal use. This feature is provided to
keep the COP watchdog timer active in the event a STOP instruction is
inadvertently executed.
6.5.1 WAIT Instruction
The WAIT instruction places the MCU in a low-power mode, which
consumes more power than stop mode. In wait mode, the PH2 clock is
halted, suspending all processor and internal bus activity. Internal timer
clocks remain active, permitting interrupts to be generated from the 16-
bit timer and reset to be generated from the COP watchdog timer.
Execution of the WAIT instruction automatically clears the I bit in the
condition code register, enabling the external interrupt. All other
registers, memory, and input/output lines remain in their previous state.
If the 16-bit timer interrupt is enabled, it will cause the processor to exit
wait mode and resume normal operation. The 16-bit timer may be used
to generate a periodic exit from the wait mode. Wait mode may also be
exited when an external interrupt or reset occurs.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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