參數(shù)資料
型號: MC68HC05P1AP
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28
封裝: PLASTIC, DIP-28
文件頁數(shù): 89/124頁
文件大?。?/td> 3724K
代理商: MC68HC05P1AP
16-Bit Timer
Timer
MC68HC05P1A Rev. 3.0
General Release Specification
16-Bit Timer
NON-DISCLOSURE
AGREEMENT
REQUIRED
Figure 8-4. State Timing Diagram for Timer Overflow
The free-running counter is initialized to $FFFC during reset. It is a read-
only register. During power-on reset (POR), the counter is initialized to
$FFFC and begins counting after the oscillator startup delay. Because
the counter is 16 bits preceded by a fixed divide-by-four prescaler, the
value in the counter repeats every 262,144 PH2 clock cycles (524,288
oscillator cycles). When the free-running counter rolls over from $FFFF
to $0000, the timer overflow flag bit (TOF) in register TSR is set. When
counter rollover occurs, an interrupt also can be enabled by setting the
timer overflow interrupt enable bit (TOIE) in register TCR.
Figure 8-5. State Timing Diagram for Timer Reset
$FFFE
$FFFF
$0000
$0001
$0002
16-BIT FREE-
RUNNING
COUNTER
TIMER
OVERFLOW
FLAG (TOF)
PH2
CLOCK
NOTE: The TOF bit is set at timer state T11 (transition of counter from $FFFF to $0000). It is cleared by reading the timer status
register (TSR) during the high portion of the PH2 clock followed by reading the LSB of the counter register pair (TCRL).
NOTE: The counter and control registers are the only 16-bit timer registers affected by reset.
PH2 CLOCK
INTERNAL
RESET
16-BIT FREE-
RUNNING
COUNTER
RESET
(EXTERNAL OR
OTHER)
$FFFC
$FFFD
$FFFE
$FFFF
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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