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| 型號(hào)： | MC68HC05P1AP |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁(yè)數(shù)： | 58/124頁(yè) |
| 文件大?。?/td> | 3724K |
| 代理商： | MC68HC05P1AP |
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Interrupts
Reset Interrupt Sequence
MC68HC05P1A — Rev. 3.0
General Release Specification
Interrupts
NON-DISCLOSURE
AGREEMENT
REQUIRED
4.3 Reset Interrupt Sequence
The reset function is not in the strictest sense an interrupt; however, it is
acted upon in a similar manner, as shown in Figure 4-1. A low level input
on the RESET pin or internally generated RST signal causes the
program to vector to its starting address, which is specified by the
contents of memory locations $1FFE and $1FFF. The I bit in the
condition code register is also set. The MCU is configured to a known
state during a reset, as described in Section 5. Resets.
4.4 Software Interrupt (SWI)
The SWI is an executable instruction. It is also a non-maskable interrupt
since it is executed regardless of the state of the I bit in the CCR. As with
any instruction, interrupts pending during the previous instruction will be
serviced before the SWI opcode is fetched. The interrupt service routine
address for the SWI instruction is specified by the contents of memory
locations $1FFC and $1FFD.
4.5 Hardware Interrupts
All hardware interrupts are maskable by the I bit in the CCR. If the I bit
is set, all hardware interrupts (internal and external) are disabled.
Clearing the I bit enables the hardware interrupts. The hardware
interrupts are explained in the following sections.
4.5.1 External Interrupt (IRQ)
The IRQ pin drives an asynchronous interrupt to the CPU. An edge
detector flip-flop is latched on the falling edge of IRQ. If either the output
from the internal edge detector flip-flops or the level on the IRQ pin is
low, a request is synchronized to the CPU to generate the IRQ interrupt.
If the edge-sensitive only mask option is selected, the output of the
internal edge detector flip-flop is sampled and the input level on the IRQ
pin is ignored. The interrupt service routine address is specified by the
contents of memory locations $1FFA and $1FFB. A block diagram of the
IRQ function is shown in Figure 4-2.
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For More Information On This Product,
Go to: www.freescale.com
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