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參數(shù)資料
| 型號(hào)： | MC68HC05K3CSDR2 |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | SSOP-20 |
| 文件頁(yè)數(shù)： | 85/132頁(yè) |
| 文件大?。?/td> | 1188K |
| 代理商： | MC68HC05K3CSDR2 |
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Technical Data
MC68HC05K3 — Revision 4.0
56
Operational Modes
MOTOROLA
Operational Modes
6.3.2 Halt Mode
Execution of the STOP instruction with a mask option to disable the stop
mode places the MCU in a low-power halt mode, which consumes more
power than stop mode. In halt mode, the internal processor clock is
halted, suspending all processor and internal bus activity. Internal timer
clocks remain active, permitting interrupts to be generated from the timer
or a reset to be generated from the COP watchdog timer. Execution of
the STOP instruction in the halt mode automatically clears the I bit in the
condition code register and sets the IRQE enable bit in the IRQ
status/control register so that the IRQ external interrupt is enabled. All
other registers, memory, and input/output lines remain in their previous
states.
If timer interrupts are enabled, a timer interrupt causes the processor to
exit halt mode and resume normal operation. Halt mode also can be
exited when an external IRQ or external RESET occurs. When exiting
halt mode, the internal processor clock resumes after a variable delay.
Depending on the mask option state, the maximum oscillator
stabilization delay is 16 or 4064 cycles of the internal processor clock.
Using the mask option to disable the STOP instruction prevents the
STOP instruction from halting the oscillator or affecting the COP
watchdog timer similar to wait mode. However, the recovery method
introduces some startup delay in the processor clock.
NOTE:
Halt mode is not intended for normal use, but is provided to keep the
COP watchdog timer active if the STOP instruction opcode is executed
inadvertently.
6.3.3 Wait Mode
The WAIT instruction places the MCU in a low-power wait mode, which
consumes more power than stop mode. In wait mode, the internal
processor clock is halted, suspending all processor and internal bus
activity. Internal timer clocks remain active, permitting interrupts to be
generated from the timer or a reset to be generated from the COP
watchdog timer. Execution of the WAIT instruction automatically clears
the I bit in the condition code register and sets the IRQE enable bit in the
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