參數(shù)資料
型號(hào)： MC68HC05K3CSDR2
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDSO20
封裝： SSOP-20
文件頁數(shù)： 68/132頁
文件大?。?/td> 1188K
代理商： MC68HC05K3CSDR2
Technical Data
MC68HC05K3 — Revision 4.0
40
Interrupts
MOTOROLA
Interrupts
4.3 Central Processor Unit (CPU) Interrupt Processing
Interrupts cause the processor to save register contents on the stack
and to set the interrupt mask (I bit) to prevent additional interrupts. Unlike
RESET, hardware interrupts do not cause the current instruction
execution to be halted, but are considered pending until the current
instruction is complete.
If interrupts are not masked (I bit in the CCR is clear) and the
corresponding interrupt enable bit is set, the processor proceeds with
interrupt processing. Otherwise, the next instruction is fetched and
executed. If an interrupt occurs, the processor completes the current
instruction, stacks the current CPU register states, sets the I bit to inhibit
further interrupts, and finally checks the pending hardware interrupts. If
more than one interrupt is pending following the stacking operation, the
interrupt with the highest vector location, shown in Table 4-1, is serviced
first. The software interrupt (SWI) is executed the same as any other
instruction, regardless of the I-bit state.
When an interrupt is to be processed, the CPU fetches the address of
the appropriate interrupt software service routine from the vector table at
locations $03F8–$03FF as defined in Table 4-1.
Table 4-1. Vector Addresses for Interrupts and Reset
Register
Flag Name
Interrupts
CPU
Interrupts
Vector
Addresses
N/A
Reset
RESET
$03FE–$03FF
N/A
Software
SWI
$03FC–$03FD
ISCR
IRQF
External interrupt
IRQ
$03FA–$03FB
TSCR
TOF
Timer overow
TIMER
$03F8–$03F9
TSCR
RTIF
Real-time interrupt
TIMER
$03F8–$03F9
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