參數(shù)資料
型號(hào): MC68HC05K3CSDR2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDSO20
封裝: SSOP-20
文件頁(yè)數(shù): 106/132頁(yè)
文件大?。?/td> 1188K
代理商: MC68HC05K3CSDR2
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8-Bit Timer
Timer Registers
MC68HC05K3 — Revision 4.0
Technical Data
MOTOROLA
8-Bit Timer
75
RTIE — Real-Time Interrupt Enable Bit
The RTIE is an enable bit that allows the generation of a timer
interrupt. When the RTIE enable bit is set and the RTIF flag bit is set,
the timer interrupt is generated. The RTIE bit is cleared by reset.
TOFR — Timer Overflow Acknowledge Bit
The TOFR is an acknowledge bit that resets the TOF flag bit. Writing
a logical 1 to the TOFR clears the TOF flag bit. Reading the TOFR
always returns a logical 0. This bit is unaffected by reset.
RTIFR — Real-Time Interrupt Acknowledge Bit
The RTIFR is an acknowledge bit that resets the RTIF flag bit. Writing
a logical 1 to the RTIFR clears the RTIF flag bit. Reading the RTIFR
always returns a logical 0. This bit is unaffected by reset.
RT1:RT0 — Real-Time Interrupt Rate Select Bit
The RT0 and RT1 control bits select one-of-four taps for the real-time
interrupt circuit. Table 8-1 shows the available interrupt rates with
several fOP values. Both the RT0 and RT1 control bits are set by
reset, selecting the lowest periodic rate and therefore the maximum
time in which to alter these bits if necessary. Care should be taken
when altering RT0 and RT1 if the time-out period is imminent or
uncertain. If the selected tap is modified during a cycle in which the
counter is switching, an RTIF can be missed or an additional RTIF can
be generated. To avoid problems, the COP should be cleared just
prior to changing RTI taps.
Table 8-1. RTI Rates and COP Reset Times
RT1
and RT0
RTI
Rate
RTI Period
(f
OP = 2 MHz)
COP Timeout
Period
(
± 1 RTI Period)
Minimum COP
Timeout Period
(f
OP = 2 MHz)
00
f
OP ÷ 2
14
8.2 ms
8 x RTI period
57.3 ms
01
f
OP ÷ 2
15
16.4 ms
8 x RTI period
114.7 ms
10
f
OP ÷ 2
16
32.8 ms
8 x RTI period
229.4 ms
11
f
OP ÷ 2
17
65.5 ms
8 x RTI period
458.8 ms
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