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參數(shù)資料
| 型號： | MC68HC05E0FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 55/96頁 |
| 文件大?。?/td> | 890K |
| 代理商： | MC68HC05E0FN |
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6
MC68HC05E0
MOTOROLA
6-7
PARALLEL INPUT/OUTPUT PORTS
6.5
Other Port Considerations
All ports are latched with the bus timing signal P02 (especially for inputs).
All output ports can emulate open-drain outputs. This is achieved by writing a zero to the relevant
output port latch. By toggling the corresponding data direction bit, the port pin will either be an
output zero or tri-state (an input). Refer to Figure 6-5.
When using a port pin as an open-drain output, certain precautions must be taken in the user
software. If a read-modify-write instruction is used on a port where the open-drain is assigned and
the pin at this time is programmed as an input, it will read it as a “one”. The read-modify-write
instruction will then write this “one” into the output data latch on the next cycle. This would cause
the open-drain pin not to output a “zero” when desired.
Note:
“Open-drain” outputs should not be pulled above VDD.
Figure 6-4 Port E Structure
Port E
Data
Register
($0004)
I C
Control
Logic
2
SI Data Register ($000F)
SPI
Control
Logic
Selection
Logic
E0
E1
E2
E3
PS1
Port E
Pads
PS0
59
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