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參數(shù)資料
| 型號： | MC68HC05E0FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 38/96頁 |
| 文件大小： | 890K |
| 代理商： | MC68HC05E0FN |
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4
MC68HC05E0
MOTOROLA
4-7
RESETS, INTERRUPTS AND LOW POWER MODES
4.2.2
Non-Maskable Software interrupt (SWI)
The software interrupt SWI is an executable instruction and a non-maskable interrupt: it is
executed regardless of the state of the I bit in the CCR. If the I bit is zero (interrupts enabled), SWI
is executed after interrupts which were pending when the SWI was fetched, but before interrupts
generated after the SWI was fetched. The SWI interrupt service routine address is specied by
the contents of memory locations $FFFC and $FFFD.
4.2.3
Maskable Hardware Interrupts
If the interrupt mask bit (I bit) of the CCR is set, all maskable interrupts (internal and external) are
disabled. Clearing the I bit enables interrupts.
Note:
The internal interrupt latch is cleared in the rst part of the interrupt service routine;
therefore, one external interrupt pulse could be latched and serviced as soon as the I
bit is cleared.
4.2.3.1
External Interrupt (INTX)
The interrupt request is latched immediately following the selected edge on the INTX pin. It is then
synchronized internally and serviced by the routine that has its start address contained in memory
locations $FFFA and $FFFB. The External Interrupt Mask bit (INTMX) in the Interrupt Control
Register ($000E) allows this interrupt to be masked from the processor.
4.2.3.2
Real Time Interrupt
The interrupt request is latched when the Real Time Interrupt Timer times out. It is then
synchronized internally and serviced by the routine that has its start address contained in memory
locations $FFFA and $FFFB. The Real Time Interrupt Enable bit (RTIE) in the RTI Control Register
($0018) allows this interrupt to be masked from the processor.
4.2.3.3
Port C Wake-up
The interrupt request is latched when a dened Wake-up signal appears on one of the pins of Port
C. It is then synchronized internally and serviced by the routine that has its start address contained
in memory locations $FFFA and $FFFB. The Wake-up Enable bits (WEn) in the Wake-up Enable
Register ($0013) allow these interrupts to be masked from the processor.
43
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