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參數(shù)資料
| 型號： | MC68HC05E0FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 14/96頁 |
| 文件大?。?/td> | 890K |
| 代理商： | MC68HC05E0FN |
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2
MC68HC05E0
MOTOROLA
2-5
FUNCTIONAL PIN DESCRIPTION
2.10
INTX
INTX is an input pin for external interrupt sources. The interrupt type (edge or level sensitive),
value (high of low), as well as interrupt masking can be selected via the Interrupt Control Register.
2.11
TS
The active low TS input pin allows the internal timer functions Timer A and Timer B to be halted.
This feature is particularly useful in the emulation environment.
2.12
TEST
The TEST input is only required for factory testing of internal functions. It must not be used during
normal operation and must always be connected to VSS.
2.13
Expanded Address Bus (A0 – A12)
Address lines A0 to A12 are always available at these output-only pins and are directly controlled
by the processor core. They are intended for accessing external memory. Additional external
memory can be addressed by using these lines in conjunction with optional address lines A13 –
A15, available on Port D.
2.14
External Data Bus (D0 – D7)
Data signals D0 to D7 are bidirectional signals and permit direct access to the internal data bus.
The data bus lines can be congured as input only lines by clearing the XROM bit in the Timer
Control Register ($000C); this feature is included to help minimise RFI.
Note:
The address bus lines (A0 – A12) and the data bus lines (D0 – D7) have been designed
to have a maximum driving current of 2mA, in order to minimise HF disturbance. The
input and output signal levels are CMOS and TTL compatible.
21
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