參數(shù)資料
型號: MC68HC05C9ECP
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40
封裝: PLASTIC, DIP-40
文件頁數(shù): 95/106頁
文件大?。?/td> 659K
代理商: MC68HC05C9ECP
Control Timing
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1
Freescale Semiconductor
89
Figure 12-5. External Interrupt Timing
Figure 12-6. Stop Recovery Timing Diagram
IRQ
tILIH
tILIL
tILIH
IRQ PIN
IRQ1
IRQN
.
a. Edge-Sensitive Trigger Condition. The minimum pulse width (tILIH) is either 125 ns (fOP = 2.1 MHz)
or 250 ns (fOP = 1 MHz). The period tILIL should not be less than the number of tCYC cycles it takes to
execute the interrupt service routine plus 19 tCYC cycles.
b. Level-Sensitive Trigger Condition. If after servicing an interrupt the IRQ remains low,
(INTERNAL)
NORMALLY
USED WITH
WIRED-OR
CONNECTION
the next interrupt is recognized.
tILIH
4064 tCYC
OSC(1)
tRL
RESET
IRQ(2)
IRQ(3)
INTERNAL
CLOCK
Notes:
1. Represents the internal clocking of the OSC1 pin
2. IRQ pin edge-sensitive mask option
3. IRQ pin level- and edge-sensitive mask option
4. RESET vector address shown for timing example
RESET OR INTERRUPT
VECTOR FETCH
$3FFE
$3FFF4
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