參數(shù)資料
型號(hào)： MC68HC05C9ECP
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40
封裝： PLASTIC, DIP-40
文件頁(yè)數(shù)： 25/106頁(yè)
文件大小： 659K
代理商： MC68HC05C9ECP
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1
Freescale Semiconductor
25
Chapter 4
Interrupts
4.1 Introduction
The MC68HC05C9E microcontroller unit (MCU) can be interrupted by five different sources: four
maskable hardware interrupts, and one non-maskable software interrupt:
External signal on the IRQ pin or port B pins
16-bit programmable timer
Serial communications interface (SCI)
Serial peripheral interface (SPI)
Software interrupt instruction (SWI)
Interrupts cause the processor to save register contents on the stack and to set the interrupt mask (I bit)
to prevent additional interrupts. The return from interrupt (RTI) instruction causes the register contents to
be recovered from the stack and normal processing to resume.
Unlike RESET, hardware interrupts do not cause the current instruction execution to be halted, but are
considered pending until the current instruction is complete.
NOTE
The current instruction is the one already fetched and being operated on.
When the current instruction is complete, the processor checks all pending hardware interrupts. If
interrupts are not masked (CCR I bit clear) and if the corresponding interrupt enable bit is set, the
processor proceeds with interrupt processing; otherwise, the next instruction is fetched and executed.
If an external interrupt and a timer, SCI, or SPI interrupt are pending at the end of an instruction execution,
the external interrupt is serviced first. The SWI is executed the same as any other instruction, regardless
of the I-bit state.
Table 4-1 shows the relative priority of all the possible interrupt sources. Figure 4-1 shows the interrupt
processing flow.
4.2 Non-Maskable Software Interrupt (SWI)
The SWI is an executable instruction and a non-maskable interrupt. It is executed regardless of the state
of the I bit in the CCR. If the I bit is 0 (interrupts enabled), SWI executes after interrupts which were
pending when the SWI was fetched, but before interrupts generated after the SWI was fetched. The
interrupt service routine address is specified by the contents of memory locations $3FFC and $3FFD.
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