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參數(shù)資料

型號(hào)：	MC68HC05C9ECP
廠商：	FREESCALE SEMICONDUCTOR INC
元件分類(lèi)：	微控制器/微處理器
英文描述：	8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40
封裝：	PLASTIC, DIP-40
文件頁(yè)數(shù)：	34/106頁(yè)
文件大?。?/td>	659K
代理商：	MC68HC05C9ECP

COP During Wait Mode

MC68HC05C9E Advance Information Data Sheet, Rev. 0.1

Freescale Semiconductor

5.5 COP During Wait Mode

The COP will continue to operate normally during wait mode. The software must pull the device out of

wait mode periodically and reset the COP to prevent a system reset.

5.6 COP During Stop Mode

Stop mode disables the oscillator circuit and thereby turns the clock off for the entire device. The COP

counter will be reset when stop mode is entered. If a reset is used to exit stop mode, the COP counter will

be reset after the 4064 cycles of delay after stop mode. If an IRQ is used to exit stop mode, the COP

counter will not be reset after the 4064-cycle delay and will have that many cycles already counted when

control is returned to the program.

In the event that an inadvertent STOP instruction is executed, the COP will not provide a reset. The clock

monitor function provides protection for this situation.

5.7 Clock Monitor Reset

The clock monitor circuit can provide a system reset if the clock stops for any reason, including stop mode.

When the CME bit in the COP control register is set, the clock monitor detects the absence of the internal

bus clock for a certain period of time. The timeout period is dependent on the processing parameters and

varies from 5

s to 100 s, which implies that systems using a bus clock rate of 200 kHz or less should

not use the clock monitor.

If a slow or absent clock is detected, the clock monitor causes a system reset. The reset is issued to the

external system via the bidirectional RESET pin for four bus cycles if the clock is slow or until the clocks

recover in the case where the clocks are absent.

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