參數(shù)資料
型號(hào)： MC68HC05C9ECP
廠商： FREESCALE SEMICONDUCTOR INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40
封裝： PLASTIC, DIP-40
文件頁(yè)數(shù)： 68/106頁(yè)
文件大?。?/td> 659K
代理商： MC68HC05C9ECP
Serial Peripheral Interface (SPI)
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1
64
Freescale Semiconductor
In the master mode, the SCK pin is an output. It idles high or low, depending on the CPOL bit in the SPCR,
until data is written to the shift register, at which point eight clocks are generated to shift the eight bits of
data and then SCK goes idle again.
In a slave mode, the slave select start logic receives a logic low at the SS pin and a clock at the SCK pin.
Thus, the slave is synchronized with the master. Data from the master is received serially at the MOSI
line and loads the 8-bit shift register. After the 8-bit shift register is loaded, its data is parallel transferred
to the read buffer. During a write cycle, data is written into the shift register, then the slave waits for a clock
train from the master to shift the data out on the slave’s MISO line.
Figure 10-3 illustrates the MOSI, MISO, SCK, and SS master-slave interconnections.
Figure 10-3. Serial Peripheral Interface Master-Slave Interconnection
10.5 SPI Registers
This subsection describes the three registers in the SPI which provide control, status, and data storage
functions. These registers are:
Serial peripheral control register (SPCR)
Serial peripheral status register (SPSR)
Serial peripheral data I/O register (SPDR)
10.5.1 Serial Peripheral Control Register
The SPI control register (SPCR), shown in Figure 10-4, controls these functions:
Enables SPI interrupts
Enables the SPI system
Selects between standard CMOS or open drain outputs for port D
Selects between master mode and slave mode
Controls the clock/data relationship between master and slave
Determines the idle level of the clock pin
Address:
$000A
Bit 7
654321
Bit 0
Read:
SPIE
SPE
DWOM
MSTR
CPOL
CPHA
SPR1
SPR0
Write:
Reset:
000001
U
U = Undetermined
Figure 10-4. SPI Control Register (SPCR)
SPI SHIFT REGISTER
7 6 5 4 3 2 1 0
SPI SHIFT REGISTER
7 6 5 4 3 2 1 0
SPDR ($000C)
PD3/MOSI
PD2/MISO
PD5/SS
PD4/SCK
MASTER MCU
SLAVE MCU
I/O PORT
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