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| 型號(hào)： | MC68HC05C9ECP |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁(yè)數(shù)： | 32/106頁(yè) |
| 文件大?。?/td> | 659K |
| 代理商： | MC68HC05C9ECP |
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Computer Operating Properly (COP) Reset
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1
Freescale Semiconductor
31
Figure 5-3. COP Block Diagram
5.4.1 COP Reset Register
The COP reset register (COPRST), shown in Figure 5-4, is a write-only register used to reset the COP.
The sequence required to reset the COP timer is:
Write $55 to the COP reset register
Write $AA to the COP reset register
Both write operations must occur in the order listed, but any number of instructions may be executed
between the two write operations provided that the COP does not time out between the two writes. The
elapsed time between software resets must not be greater than the COP timeout period. If the COP
should time out, a system reset will occur and the device will be re-initialized in the same fashion as a
power-on reset or reset.
Reading this register does not return valid data.
5.4.2 COP Control Register
The COP control register (COPCR), shown in Figure 5-5, performs these functions:
Enables clock monitor function
Enables COP function
Selects timeout duration of COP timer
And flags these conditions:
COP timeout
Clock monitor reset
Address: $001D
Bit 7
6543
2
1
Bit 0
Read:
Write:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset:
00000
0
= Unimplemented
Figure 5-4. COP Reset Register (COPRST)
÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2
÷4
÷2
213
215
217
219
221
COPRST
CM0
CM1
16-BIT TIMER SYSTEM
INTERNAL
CPU
CLOCK
COP
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