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參數(shù)資料
| 型號(hào)： | MC68B912B32 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 2.5V 100ppm/Degrees C, 50uA in SOT23-3 Series (Bandgap) Voltage Reference 3-SOT-23 -40 to 125 |
| 中文描述： | 16位微控制器 |
| 文件頁數(shù)： | 83/128頁 |
| 文件大小： | 748K |
| 代理商： | MC68B912B32 |
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MC68HC912B32
MC68HC912B32TS/D
MOTOROLA
83
13 Serial Interface
The serial interface of the MC68HC912B32 consists of two independent serial I/O sub-systems: the se-
rial communication interface (SCI) and the serial peripheral interface (SPI). Each serial pin shares func-
tion with the general-purpose port pins of port S. The SCI is an NRZ type system that is compatible with
standard RS-232 systems. The SCI system has a single wire operation mode which allows the unused
pin to be available as general-purpose I/O. The SPI subsystem, which is compatible with the M68HC11
SPI, includes new features such as SS output and bidirectional mode.
13.1 Block Diagram
Figure 19 Serial Interface Block Diagram
13.2 Serial Communication Interface (SCI)
The serial communication interface on the MC68HC912B32 is an NRZ format (one start, eight or nine
data, and one stop bit) asynchronous communication system with independent internal baud rate gen-
eration circuitry and an SCI transmitter and receiver. It can be configured for eight or nine data bits (one
of which may be designated as a parity bit, odd or even). If enabled, parity is generated in hardware for
transmitted and received data. Receiver parity errors are flagged in hardware. The baud rate generator
is based on a modulus counter, allowing flexibility in choosing baud rates. There is a receiver wake-up
feature, an idle line detect feature, a loop-back mode, and various error detection features. Two port
pins provide the external interface for the transmitted data (TXD) and the received data (RXD).
SCI
I/O
SPI
D
P
SERIAL
INTERFACE
HC12B32 SI BLOCK
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
RxD
TxD
MISO/SISO
MOSI/MOMI
SCK
CS/SS
I/O
I/O
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