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參數(shù)資料
| 型號(hào)： | MC68B912B32 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 2.5V 100ppm/Degrees C, 50uA in SOT23-3 Series (Bandgap) Voltage Reference 3-SOT-23 -40 to 125 |
| 中文描述： | 16位微控制器 |
| 文件頁數(shù)： | 116/128頁 |
| 文件大小： | 748K |
| 代理商： | MC68B912B32 |
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MOTOROLA
116
MC68HC912B32
MC68HC912B32TS/D
commands, but can steal cycles from the CPU when necessary. Other BDM commands are firmware
based, and require the CPU to be in active background mode for execution. While BDM is active, the
CPU executes a firmware program located in a small on-chip ROM that is available in the standard 64-
Kbyte memory map only while BDM is active.
The BDM control logic communicates with an external host development system serially, via the BKGD
pin. This single-wire approach minimizes the number of pins needed for development support.
16.2.1 Enabling BDM Firmware Commands
BDM is available in all operating modes, but must be made active before firmware commands can be
executed. BDM is enabled by setting the ENBDM bit in the BDM STATUS register via the single wire
interface (using a hardware command; WRITE_BD_BYTE at $FF01). BDM must then be activated to
map BDM registers and ROM to addresses $FF00 to $FFFF and to put the MCU in active background
mode.
After the firmware is enabled, BDM can be activated by the hardware BACKGROUND command, by
the BDM tagging mechanism, or by the CPU BGND instruction. An attempt to activate BDM before firm-
ware has been enabled causes the MCU to resume normal instruction execution after a brief delay.
BDM becomes active at the next instruction boundary following execution of the BDM BACKGROUND
command, but tags activate BDM before a tagged instruction is executed.
In special single-chip mode, background operation is enabled and active immediately out of reset. This
active case replaces the M68HC11 boot function, and allows programming a system with blank mem-
ory.
While BDM is active, a set of BDM control registers are mapped to addresses $FF00 to $FF06. The
BDM control logic uses these registers which can be read anytime by BDM logic, not user programs.
Refer to
16.2.4 BDM Registers
for detailed descriptions.
Some on-chip peripherals have a BDM control bit which allows suspending the peripheral function dur-
ing BDM. For example, if the timer control is enabled, the timer counter is stopped while in BDM. Once
normal program flow is continued, the timer counter is re-enabled to simulate real-time operations.
16.2.2 BDM Serial Interface
The BDM serial interface requires the external controller to generate a falling edge on the BKGD pin to
indicate the start of each bit time. The external controller provides this falling edge whether data is trans-
mitted or received.
BKGD is a pseudo-open-drain pin that can be driven either by an external controller or by the MCU.
Data is transferred MSB first at 16 E-clock cycles per bit (nominal speed). The interface times out if 256
E-clock cycles occur between falling edges from the host. The hardware clears the command register
when a time-out occurs.
The BKGD pin can receive a high or low level or transmit a high or low level. The following diagrams
show timing for each of these cases. Interface timing is synchronous to MCU clocks but asynchronous
to the external host. The internal clock signal is shown for reference in counting cycles.
Figure 27
shows an external host transmitting a logic one or zero to the BKGD pin of a target
MC68HC912B32 MCU. The host is asynchronous to the target so there is a 0-to-1 cycle delay from the
host-generated falling edge to where the target perceives the beginning of the bit time. Nine target E
cycles later, the target senses the bit level on the BKGD pin. Typically the host actively drives the pseu-
do-open-drain BKGD pin during host-to-target transmissions to speed up rising edges. Since the target
does not drive the BKGD pin during this period, there is no need to treat the line as an open-drain signal
during host-to-target transmissions.
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