參數(shù)資料
型號： MC68B912B32
廠商： Motorola, Inc.
英文描述： 2.5V 100ppm/Degrees C, 50uA in SOT23-3 Series (Bandgap) Voltage Reference 3-SOT-23 -40 to 125
中文描述： 16位微控制器
文件頁數(shù)： 13/128頁
文件大小： 748K
代理商： MC68B912B32
MC68HC912B32
MC68HC912B32TS/D
MOTOROLA
13
3.3.8 External Address and Data Buses (ADDR[15:0] and DATA[15:0])
External bus pins share function with general-purpose I/O ports A and B. In single-chip operating
modes, the pins can be used for I/O; in expanded modes, the pins are used for the external buses.
In expanded wide mode, ports A and B are used for multiplexed 16-bit data and address buses. PA[7:0]
correspond to ADDR[15:8]/DATA[15:8]; PB[7:0] correspond to ADDR[7:0]/DATA[7:0].
In expanded narrow mode, ports A and B are used for the 16-bit address bus, and an 8-bit data bus is
multiplexed with the most significant half of the address bus on port A. In this mode, 16-bit data is han-
dled as two back-to-back bus cycles, one for the high byte followed by one for the low byte. PA[7:0]
correspond to ADDR[15:8] and to DATA[15:8] or DATA[7:0], depending on the bus cycle. The state of
the address pin should be latched at the rising edge of E. To allow for maximum address setup time at
external devices, a transparent latch should be used.
3.3.9 Read/Write (R/W)
In all modes this pin can be used as I/O and is a general-purpose input with an active pull-up out of
reset. If the read/write function is required it should be enabled by setting the RDWE bit in the PEAR
register. External writes will not be possible until enabled.
3.3.10 Low-Byte Strobe (LSTRB)
In all modes this pin can be used as I/O and is a general-purpose input with an active pull-up out of
reset. If the strobe function is required, it should be enabled by setting the LSTRE bit in the PEAR reg-
ister. This signal is used in write operations and so external low byte writes will not be possible until this
function is enabled. This pin is also used as TAGLO in special expanded modes and is multiplexed with
the LSTRB function.
3.3.11 Instruction Queue Tracking Signals (IPIPE1 and IPIPE0)
These signals are used to track the state of the internal instruction execution queue. Execution state is
time-multiplexed on the two signals. Refer to
16 Development Support
.
3.3.12 Data Bus Enable (DBE)
The DBE pin (PE7) is an active low signal that will be asserted low during E-clock high time. DBE pro-
vides separation between output of a multiplexed address and the input of data. When an external ad-
dress is stretched, DBE is asserted during what would be the last quarter cycle of the last E-clock cycle
of stretch. In expanded modes this pin is used to enable the drive control of external buses during ex-
ternal reads. Use of the DBE is controlled by the NDBE bit in the PEAR register. DBE is enabled out of
reset in expanded modes. This pin has an active pull-up during and after reset in single-chip modes.
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