參數(shù)資料
型號(hào): MC68B912B32
廠商: Motorola, Inc.
英文描述: 2.5V 100ppm/Degrees C, 50uA in SOT23-3 Series (Bandgap) Voltage Reference 3-SOT-23 -40 to 125
中文描述: 16位微控制器
文件頁數(shù): 37/128頁
文件大?。?/td> 748K
代理商: MC68B912B32
MC68HC912B32
MC68HC912B32TS/D
MOTOROLA
37
7 Flash EEPROM
The 32-Kbyte Flash EEPROM module for the MC68HC912B32 serves as electrically erasable and pro-
grammable, non-volatile ROM emulation memory. The module can be used for program code that must
either execute at high speed or is frequently executed, such as operating system kernels and standard
subroutines, or it can be used for static data which is read frequently. The Flash EEPROM is ideal for
program storage for single-chip applications allowing for field reprogramming.
7.1 Overview
The Flash EEPROM array is arranged in a 16-bit configuration and may be read as either bytes, aligned
words or misaligned words. Access time is one bus cycle for byte and aligned word access and two bus
cycles for misaligned word operations.
The Flash EEPROM module requires an external program/erase voltage (V
FP
) to program or erase the
Flash EEPROM array. The external program/erase voltage is provided to the Flash EEPROM module
via an external V
FP
pin. To prevent damage to the flash array, V
FP
should always be greater than or
equal to V
DD
0
.5V. Programming is by byte or aligned word. The Flash EEPROM module supports bulk
erase only.
The Flash EEPROM module has hardware interlocks which protect stored data from accidental corrup-
tion. An erase- and program-protected 2-Kbyte block for boot routines is located at $7800–$7FFF or
$F800–$FFFF depending upon the mapped location of the Flash EEPROM array. (The protected boot
block on the initial mask sets, G86W and G75R, is 1-Kbyte and is located at $7C00–$7FFF or $FC00–
$FFFF.)
7.2 Flash EEPROM Control Block
A 4-byte register block controls the Flash EEPROM module operation. Configuration information is
specified and
programmed independently from the contents of the Flash EEPROM array. At reset, the
4-byte register section starts at address $00F4.
7.3 Flash EEPROM Array
After reset, the Flash EEPROM array is located from addresses $8000 to $FFFF in single-chip mode.
In Expanded modes the Flash EEPROM array is located from address $0000 to $7FFF, however, it is
turned off. The Flash EEPROM can be mapped to an alternate address range. See
5 Operating Modes
and Resource Mapping
.
7.4 Flash EEPROM Registers
In normal modes the LOCK bit can only be written once after reset.
LOCK — Lock Register Bit
0 = Enable write to FEEMCR register
1 = Disable write to FEEMCR register
FEELCK
Flash EEPROM Lock Control Register
$00F4
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
LOCK
RESET:
0
0
0
0
0
0
0
0
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