
MOTOROLA
CENTRAL PROCESSOR UNIT
MC68336/376
4-14
USER’S MANUAL
4.8.1 M68000 Family Compatibility
It is the philosophy of the M68000 family that all user-mode programs can execute un-
changed on future derivatives of the M68000 family, and supervisor-mode programs
and exception handlers should require only minimal alteration.
The CPU32 can be thought of as an intermediate member of the M68000 Family. Ob-
ject code from an MC68000 or MC68010 may be executed on the CPU32. Many of the
instruction and addressing mode extensions of the MC68020 are also supported. Re-
fer to the
CPU32 Reference Manual (CPU32RM/AD) for a detailed comparison of the
CPU32 and MC68020 instruction set.
4.8.2 Special Control Instructions
Low-power stop (LPSTOP) and table lookup and interpolate (TBL) instructions have
been added to the MC68000 instruction set for use in controller applications.
4.8.2.1 Low-Power Stop (LPSTOP)
In applications where power consumption is a consideration, the CPU32 forces the de-
vice into a low-power standby mode when immediate processing is not required. The
low-power stop mode is entered by executing the LPSTOP instruction. The processor
remains in this mode until a user-specified (or higher) interrupt level or reset occurs.
4.8.2.2 Table Lookup and Interpolate (TBL)
To maximize throughput for real-time applications, reference data is often precalculat-
ed and stored in memory for quick access. Storage of many data points can require
an inordinate amount of memory. The table lookup instruction requires that only a
sample of data points be stored, reducing memory requirements. The TBL instruction
recovers intermediate values using linear interpolation. Results can be rounded with a
round-to-nearest algorithm.
NOTES:
1. Privileged instruction.
TBLSN/TBLUN
<ea>, Dn
Dym : Dyn, Dn
8, 16, 32
Dyn
Dym Temp
(Temp
Dn [7 : 0]) / 256 Temp
Dym
+ Temp Dn
TRAP
#<data>
none
SSP
2 SSP; format/vector offset (SSP);
SSP
4 SSP; PC (SSP); SR (SSP);
vector address
PC
TRAPcc
none
#<data>
none
16, 32
If cc true, then TRAP exception
TRAPV
none
If V set, then overflow TRAP exception
TST
<ea>
8, 16, 32
Source
0, to set condition codes
UNLK
An
32
An
SP; (SP) An, SP + 4 SP
Table 4-2 Instruction Set Summary (Continued)
336376UMBook Page 14 Friday, November 15, 1996 2:09 PM