
MOTOROLA
CONFIGURABLE TIMER MODULE 4
MC68336/376
10-16
USER’S MANUAL
10.9.8 PWM Frequency
The relationship between the PWM output frequency (fPWM) and the MCU system
clock frequency (fsys) is given by the following equation:
where NCLOCK is the divide ratio specified by the CLK[2:0] field in PWMSIC and
NPERIOD is the period specified by PWMA1.
The minimum PWM output frequency achievable with a specified number of bits of res-
olution for a given system clock frequency is:
where NCPSM is the CPSM divide ratio of two or three.
Similarly, the maximum PWM output frequency achievable with a specified number of
bits of resolution for a given system clock frequency is:
Tables 10-5 and 10-6 summarize the minimum pulse widths and frequency ranges
available from the PWMSM based on the CPSM system clock divide ratio and a
system clock frequency of 20.97 MHz.
Table 10-5 PWM Pulse and Frequency Ranges (in Hz) Using
÷ 2 Option (20.97 MHz)
fsys
Divide
Ratio
Minimum
Pulse
Width
Bits of Resolution
16
15
14
13
12
11
10
987654321
÷ 2
0.095
s
160
320
640
1280
2560
5120
10239
20479
40957
81914
164K
328K
655K
1311K
2621K
5243K
÷ 4
0.191
s
80
160
320
640
1280
2560
5120
10239
20479
40957
81914
164K
328K
655K
1311K
2621K
÷ 8
0.381
s
40
80
160
320
640
1280
2560
5120
10239
20479
40957
81914
164K
328K
655K
1311K
÷ 16
0.763
s
20
40
80
160
320
640
1280
2560
5120
10239
20479
40957
81914
164K
328K
655K
÷ 32
1.53
s
10
20
40
80
160
320
640
1280
2560
5120
10239
20479
40957
81914
164K
328K
÷ 64
3.05
s
5
10
20
40
80
160
320
640
1280
2560
5120
10239
20479
40957
81914
164K
÷ 128
6.10
s
2.5
5
10
20
40
80
160
320
640
1280
2560
5120
10239
20479
40957
81914
÷ 512
24.42
s
0.6
1.3
2.5
5
10
20
40
80
160
320
640
1280
2560
5120
10239
20479
Table 10-6 PWM Pulse and Frequency Ranges (in Hz) Using
÷ 3 Option (20.97 MHz)
fsys
Divide
Ratio
Minimum
Pulse
Width
Bits of Resolution
16
15
14
13
12
11
10
987654321
÷ 3
0.179
s
107
224
427
853
1707
3413
6826
13652
27305
54609
109K
218K
437K
874K
1748K
3495K
÷ 6
0.358
s
53
107
224
427
853
1707
3413
6826
13652
27305
54609
109K
218K
437K
874K
1748K
÷ 12
0.715
s
27
53
107
224
427
853
1707
3413
6826
13652
27305
54609
109K
218K
437K
874K
÷ 24
1.431
s
13
27
53
107
224
427
853
1707
3413
6826
13652
27305
54609
109K
218K
437K
÷ 48
2.861
s
7
13
27
53
107
224
427
853
1707
3413
6826
13652
27305
54609
109K
218K
÷ 96
5.722
s
3
7
13
27
53
107
224
427
853
1707
3413
6826
13652
27305
54609
109K
÷ 192
11.44
s
2
3
7
13
27
53
107
224
427
853
1707
3413
6826
13652
27305
54609
÷ 768
45.78
s
0.4
0.8
2
3
7
13
27
53
107
224
427
853
1707
3413
6826
13652
f
PWM
f
sys
N
CLOCK
N
PERIOD
-----------------------------------------------
=
Minimum f
PWM
f
sys
256N
CPSM
2
Bits of Resolution
-----------------------------------------------------------------------
=
Maximum f
PWM
f
sys
N
CPSM
2
Bits of Resolution
-------------------------------------------------------------
=
336376UMBook Page 16 Friday, November 15, 1996 2:09 PM