
MC68336/376
MOTOROLA
USER’S MANUAL
I-11
clock (QCLK) 8-14
conversion characteristics (operating) A-30
electrical characteristics (operating)
AC A-29
DC A-28
features 3-2
maximum ratings A-27
pin functions diagram 8-3
registers
control register 0 (QACR0) 8-2, 8-28, D-31
control register 1 (QACR0) 8-2, 8-28
control register 1 (QACR1) D-32
control register 2 (QACR0) 8-2, 8-28
control register 2 (QACR2) D-33
conversion command word table (CCW) D-37
interrupt register (QADCINT) 8-2, D-29
module configuration register (QADCMCR) 8-2,
8-6, D-28
port
A data register (PORTQA) 8-2
B data register (PORTQB) 8-2
data direction register (DDRQA) 8-2
QA data direction register (DDRQA) D-30
QA data register (PORTQA) D-30
QB data register (PORTQB) D-30
result word table D-39
status register (QASR) 8-2, 8-28, D-35
test register (QADCTEST) 8-2, D-29
QADCINT 8-2, D-29
QADCMCR 8-2, 8-6, D-28
QADCTEST 8-2, D-29
QASR 8-2, 8-28, D-35
QCLK 8-14, 8-23
frequency 8-24
QDEC 11-10
QILR 9-2, D-41
QIVR 9-2, D-41
QOM 11-11
QS D-36
QSM
address map 9-2, D-40
block diagram 9-1
features 3-2
general 9-1
initialization sequence 9-30
interrupts 9-3
pin function 9-4, D-48
QSPI 9-5
operating modes 9-9
operation 9-8
pins 9-8
RAM 9-7
registers 9-6
reference manual 9-1
registers
command RAM (CR) D-54
global registers 9-2
interrupt
level register (QILR) 9-2, D-41
vector register (QIVR) 9-2, D-41
test register (QTEST) 9-2
module configuration register (QSMCR) D-40
pin control registers 9-4
port QS
data direction register (DDRQS) 9-4,
D-47
data register (PORTQS) 9-4, D-46
pin assignment register (PQSPAR)
D-47
QSPI
control register 0 (SPCR0) D-48
control register 1 (SPCR1) D-50
control register 2 (SPCR2) D-51
control register 3 (SPCR3) D-52
status register (SPSR) D-52
receive data RAM (RR) D-53
SCI
control register 0 (SCCR0) D-42
control register 1 (SCCR1) D-43
data register (SCDR) D-46
status register (SCSR) D-45
test register (QTEST) D-41
transmit data RAM (TR) D-54
types 9-2
SCI 9-21
operation 9-24
pins 9-24
registers 9-21
QSMCR D-40
QSPI 9-1, 9-5
block diagram 9-5
enable (SPE) D-50
finished flag (SPIF) D-53
initialization operation 9-10
loop mode (LOOPQ) D-52
master operation flow 9-11
operating modes 9-9
master mode 9-9, 9-16
wraparound mode 9-19
slave mode 9-9, 9-19
wraparound mode 9-20
operation 9-8
peripheral chip-selects 9-20
pins 9-8
RAM 9-7
command RAM 9-8
receive RAM 9-7
transmit RAM 9-7
registers 9-6
control registers 9-6
status register 9-7
timing A-23
master A-24
slave A-25
QTEST 9-2, D-41
Quadrature decode (QDEC) 11-10
Quad-word data 4-4
Queue 8-16
pointers
completed queue pointer (CPTQP) 9-8
336376UMBook Page 11 Friday, November 15, 1996 2:09 PM