
MC68336/376
STANDBY RAM WITH TPU EMULATION
MOTOROLA
USER’S MANUAL
12-1
SECTION 12 STANDBY RAM WITH TPU EMULATION
The standby RAM module with TPU emulation capability (TPURAM) consists of a
control register block and a 3.5-Kbyte array of fast (two system clock) static RAM,
which is especially useful for system stacks and variable storage. The TPURAM re-
sponds to both program and data space accesses. The TPURAM can also be used to
emulate TPU microcode ROM.
12.1 General
The TPURAM can be mapped to the lower 3.5 Kbytes of any 4-Kbyte boundary in the
address map, but must not overlap the module control registers as overlap makes the
registers inaccessible. Data can be read or written in bytes, words or long words. The
TPURAM is powered by VDD in normal operation. During power-down, TPURAM con-
tents can be maintained by power from the VSTBY input. Power switching between
sources is automatic.
12.2 TPURAM Register Block
There are three TPURAM control registers: the TPURAM module configuration regis-
ter (TRAMMCR), the TPURAM test register (TRAMTST), and the TPURAM base ad-
dress and status register (TRAMBAR). To protect these registers from accidental
modification, they are always mapped to supervisor data space.
The TPURAM control register block begins at address $7FFB00 or $FFFB00, depend-
ing on the value of the module mapping (MM) bit in the SIM configuration register
(SIMCR). Refer to 5.2.1 Module Mapping for more information on how the state of
MM affects the system.
The TPURAM control register block occupies eight bytes of address space. Unimple-
mented register addresses are read as zeros, and writes have no effect. Refer to D.9
Standby RAM Module with TPU Emulation Capability (TPURAM) for register block
address map and register bit/field definitions.
12.3 TPURAM Array Address Mapping
The base address and status register TRAMBAR specifies the TPURAM array base
address in the MCU memory map. TRAMBAR[15:4] specify the 12 high-order bits of
the base address. The TPU bus interface unit compares these bits to address lines
ADDR[23:12]. If the two match, then the low order address lines and the SIZ[1:0] sig-
nals are used to access the RAM location in the array.
The RAM disable (RAMDS) bit, the LSB of TRAMBAR, indicates whether the
TPURAM array is active (RAMDS = 0) or disabled (RAMDS = 1). The array is disabled
coming out of reset and remains disabled if the base address field is programmed with
an address that overlaps the address of the module control register block. Writing a
valid base address to TRAMBAR[15:4] clears RAMDS and enables the array.
336376UMBook Page 1 Friday, November 15, 1996 2:09 PM