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| 型號(hào)： | MC68322FT16 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 16.667 MHz, RISC PROCESSOR, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 264/283頁(yè) |
| 文件大小： | 1602K |
| 代理商： | MC68322FT16 |
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DRAM Controller
7-2
MC68322 USER’S MANUAL
MOTOROLA
Because each DRAM register contains a size field, each DRAM bank can be individually
programmed for a different size or disabled entirely. The available sizes are either 512K, 2M,
or 8M, depending on the size field’s encoding. There are no limitations in the ordering of
bank sizes. Table 7-1 lists the size field encodings and the equivalent DRAM bank sizes.
The base address field, contained in each DRAM register, allows the six DRAM banks to be
individually located at any location in the 256-byte memory map. The DRAM register base
address field contains bits 27–19 of the corresponding DRAM bank’s starting address.
These DRAM banks can be contiguous to or disjointed from each other, as required by the
operating environment. Even though the DRAM bank can be any size, the starting address
must be unique, non-overlapping, and located on an address boundary equal to its size. For
example, an 8M DRAM bank must be on an 8M address boundary. DRAM address space
can, however, overlap with other registers, ROM, or I/O space. In case of an overlap, DRAM
has the lowest priority.
7.1.2 ROM Mode
The MC68322 DRAM controller ‘‘ROM mode’’ is available in the G59B Mask Set. The ROM
mode of operation causes the selected DRAM channel to run with extended cycle times
while the remainder of the channels operate at full speed. This will place font ROMs on one
of the DRAM channels with only an external latch required to demultiplex the address
signals. By placing the font ROMs on one of the DRAM channels, the MC68322 RGP will
have direct access to font data, which eliminates the need for a font cache, thus reducing
overall system DRAM requirements. ROM mode is selected for a particular DRAM channel
by setting the ROM mode bit in the corresponding DRAM register (see Figure 7-1 for
details).
7.1.2.1 FUNCTIONAL DESCRIPTION. When the ROM mode is selected for one of the
DRAM channels, the accesses to that channel are extended. Each initial and burst access
is extended by one CLK1 period (two CLK2 periods). For example, in timing mode 1 the
normal DRAM access time in CLK1s would be 4:2:2:2...; but when the ROM mode is
selected, the access time becomes 5:3:3:3... for that particular channel. This timing
relaxation in the ROM mode allows ROMs (which typically have longer access times than
DRAM) to operate effectively on one (or more) of the DRAM channels.
Table 7-1. DRAM Size Options
ENCODING
DRAM BANK ORGANIZATION
00
Disabled (No Size)
01
256 Kbit
× 16 (512K)
10
1 Mbit
× 16 (2M)
11
4 Mbit
× 16 (8M)
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Freescale Semiconductor, Inc.
For More Information On This Product,
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