
Signal Descriptions
MOTOROLA
MC68322 USER’S MANUAL
2-7
2.5 DRAM INTERFACE
The following signals control the DRAM bus operation:
PIN NAME
DESCRIPTION
MA10–MA0
Memory Address Bus—These 11 output only signals connect to the internally multiplexed DRAM address bus.
They directly drive the memory address bus to a DRAM array. The low-order address signals change to provide
bursting capability. See Table 2-3 for a list of DRAM address multiplexing values.
MD15–MD0
Memory Data Bus—This signal connects to a 16-bit bidirectional three-stateable memory data bus. The
memory data bus is used to transfer byte- and word-sized data to and from DRAM.
RAS5-RAS0
Row Address Strobe—These output signals provide row address strobes for external DRAM. RASx asserts
when a memory reference occurs that is internally decoded for the DRAM bank(s).
CAS1-CAS0
Column Address Strobe—These output signals provide the column address strobe timing for the external
DRAM. The CAS1 signal asserts when a byte write operation occurs to the upper memory data bus (MD15-
MD8). CAS0 asserts when a byte write operation occurs to the lower memory data bus (MD7-MD0). However,
both CAS1 and CAS0 assert for byte-sized read operations and word-sized read and write operations.
WE
Write Enable—This output signal asserts when an external DRAM access write cycle is initiated providing the
write control for external DRAM.
Table 2-3. DRAM Address Multiplexer
ROW
ADDRESS
COLUMN
ADDRESS
MEMORY
ADDRESS
DRAM SIZE
× 16 BITS
A10
A01
MA0
4 Mbit, 1 Mbit, 256 Kbit
A11
A02
MA1
4 Mbit, 1 Mbit, 256 Kbit
A12
A03
MA2
4 Mbit, 1 Mbit, 256 Kbit
A13
A04
MA3
4 Mbit, 1 Mbit, 256 Kbit
A14
A05
MA4
4 Mbit, 1 Mbit, 256 Kbit
A15
A06
MA5
4 Mbit, 1 Mbit, 256 Kbit
A16
A07
MA6
4 Mbit, 1 Mbit, 256 Kbit
A17
A08
MA7
4 Mbit, 1 Mbit, 256 Kbit
A18
A09
MA8
4 Mbit, 1 Mbit, 256 Kbit
A20
A19
MA9
4 Mbit, 1 Mbit
A22
A21
MA10
4 Mbit
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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