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| 型號(hào)： | MC68322FT16 |
| 廠(chǎng)商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 16.667 MHz, RISC PROCESSOR, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 243/283頁(yè) |
| 文件大?。?/td> | 1602K |
| 代理商： | MC68322FT16 |
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Interrupt and Exception Handling
MOTOROLA
MC68322 USER’S MANUAL
5-3
The interrupt level field reflects the interrupt priority level for that module. Level 7 is the
highest priority, level 1 is the lowest, and level 0 indicates that no interrupt is requested. If
an event occurs and causes the same level of interrupt as is currently being serviced (at the
same time an interrupt of that level is being cleared) the interrupt level will become active
again after two clocks. The interrupt level to the core could change if the priority level of an
active interrupt is changed. To avoid potential problems, priority levels should be changed
only while the corresponding interrupt is masked. Some interrupt event registers have status
bits in addition to the interrupt bits. These status bits cannot cause an interrupt to the core.
However, the software can read them at any time to obtain more information about the
module’s status.
5.1.2 Software Interrupts
There are seven independent software interrupts that can be set and cleared under software
control; each corresponding to levels 7 through 1. Software can read the software interrupt
event register for status information (or write to it to clear) or set an interrupt. Like the basic
format for each module’s interrupt event registers described above, the software interrupt
event register contains an enable field, several software status fields, and the software
interrupt event bits. Figure 5-1 illustrates the software interrupt event register.
Figure 5-1. Software Interrupt Event Register
Software interrupts are set by writing to the bits of the software interrupt event register’s SET
field. Writing a 1 to Bit 0 of the SET field generates a level 1 interrupt, Bit 1 a level 2, and so
on. The EVENT field reflects the state of the pending software interrupt. Software interrupts
can be set at any time and multiple interrupts can be set at the same time, if needed.
However, keep in mind that setting an interrupt that has already been set will have no effect.
Software interrupts are cleared by writing the EVENT field. Each bit corresponds to one of
the seven software interrupts. Writing a 1 to a bit position will clear that software interrupt,
while a zero in a bit position has no effect. For Bit 0, writing a 1 clears a level 1 interrupt, for
Bit 6 writing a 1 clears a level 2 interrupt, and so on. The interrupt service routine must clear
its interrupt to avoid another interrupt when the routine completes.
= RESERVED
15
14
13
12
11
10
9
8
7
65432
1
0
15
14
13
12
11
10
9
8
7
65432
1
0
ENABLE
00FFF790
00FFF792
00FFF794
EVENT
SET
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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