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參數(shù)資料
| 型號(hào)： | MC68322FT16 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 16.667 MHz, RISC PROCESSOR, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 214/283頁(yè) |
| 文件大?。?/td> | 1602K |
| 代理商： | MC68322FT16 |
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Signal Descriptions
2-6
MC68322 USER’S MANUAL
MOTOROLA
2.4 EXTERNAL BUS MASTER INTERFACE
The following signals control the MC68322 bus operation.
PIN NAME
DESCRIPTION
AS
Address Strobe—The active low AS signal indicates a valid address on the address bus. AS is an output when
the core or internal DMA initiates an access on the MC68322 bus and an input when an external bus master
controls the MC68322 bus.
R/W
Read/Write—This signal defines a data bus transfer as a read (active high) or write cycle (active low). R/Wis
an output when the core or internal DMA initiates an access on the MC68322 bus, and an input when an external
bus master has control of the MC68322 bus.
EDTACK
External Bus Master Data Transfer Acknowledge—This output signal is sent to an external bus master to
indicate that the data transfer is complete. When EDTACK is recognized during a read cycle, the external bus
master latches the data and terminates the bus cycle. When EDTACK is recognized during a write cycle, the
bus cycle is terminated.
BR
Bus Request—This active low input is ORed with all other devices that can be bus masters. This active-low
input signal informs the core that another device is ready to be the bus master.
BG
Bus Grant—This active low output indicates to all other potential bus masters that the MC68322 bus is
available. BG will assert after the assertion of BR, but only after all bus cycles have terminated.
CS7-CS0
Chip-Select—These signals are output only and can be programmed to provide from 256K to 64M decode.
These signals continue to function as they are programmed when an alternate bus master has control of the
MC68322 bus.
RD
Read—This signal is an output only strobe that is asserted during a read operation on the MC68322 bus. A read
cycle can be initiated by the core, internal DMA, or external bus master. The read strobe remains negated during
an MC68322 bus write cycle.
WRU
Upper Write Strobe—This strobe is an output only signal that is asserted during a write operation on the
MC68322 bus. A write cycle can be initiated by the core, internal DMA, or external bus master. The upper write
strobe asserts during all word write operations and during byte write operations to the upper portion of the data
bus (D15-D8). WRU remains negated during a read and a lower byte write cycle.
WRL
Lower Write Strobe—This strobe is an output only signal that asserts during a write operation on the MC68322
bus. A write cycle can be initiated by the core, internal DMA, or external bus master. The lower write strobe
asserts during all word write operations and during byte write operations to the lower portion of the data bus (D7-
D0). WRL remains negated during a read and an upper byte write cycle.
WAIT
Wait—This input only signal that extends an MC68322 bus cycle beyond the programmed values. Be aware that
WAIT can only prolong bus cycles for chip-select banks.
IRQ1-IRQ0
External Interrupt Request—These input only signals have programmable assertion levels and are used to
connect external interrupting devices to the MC68322. These two signals are sent through the internal interrupt
controller before posting an interrupt to the core.
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Freescale Semiconductor, Inc.
For More Information On This Product,
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