
56F8357 Technical Data, Rev. 8.0
4
 Freescale Semiconductor
Preliminary
Part 1: Overview  . . . . . . . . . . . . . . . . . . . . . . .5
1.1. 56F8357/56F8157 Features . . . . . . . . . . . . . 5
1.2. Device Description . . . . . . . . . . . . . . . . . . . . 7
1.3. Award-Winning Development Environment  . 9
1.4. Architecture Block Diagram  . . . . . . . . . . . . 10
1.5. Product Documentation  . . . . . . . . . . . . . . . 14
1.6. Data Sheet Conventions  . . . . . . . . . . . . . . 14
Part 2: Signal/Connection Descriptions . . .15
2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2. Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . 18
Part 3: On-Chip Clock Synthesis (OCCS) . .38
3.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.2. External Clock Operation . . . . . . . . . . . . . . 38
3.3. Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Part 4: Memory Map  . . . . . . . . . . . . . . . . . . .40
4.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.2. Program Map  . . . . . . . . . . . . . . . . . . . . . . . 41
4.3. Interrupt Vector Table . . . . . . . . . . . . . . . . . 43
4.4. Data Map  . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.5. Flash Memory Map . . . . . . . . . . . . . . . . . . . 46
4.6. EOnCE Memory Map . . . . . . . . . . . . . . . . . 48
4.7. Peripheral Memory Mapped Registers . . . . 49
4.8. Factory Programmed Memory  . . . . . . . . . . 75
Part 5: Interrupt Controller (ITCN) . . . . . . . .76
5.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.3. Functional Description  . . . . . . . . . . . . . . . . 76
5.4. Block Diagram  . . . . . . . . . . . . . . . . . . . . . . 78
5.5. Operating Modes  . . . . . . . . . . . . . . . . . . . . 78
5.6. Register Descriptions . . . . . . . . . . . . . . . . . 79
5.7. Resets  . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Part 6: System Integration Module (SIM)  .106
6.1. Overview  . . . . . . . . . . . . . . . . . . . . . . . . . 106
6.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.3. Operating Modes  . . . . . . . . . . . . . . . . . . . 107
6.4. Operation Mode Register . . . . . . . . . . . . . 108
6.5. Register Descriptions . . . . . . . . . . . . . . . . 108
6.6. Clock Generation Overview  . . . . . . . . . . . 121
6.7. Power Down Modes Overview . . . . . . . . . 122
6.8. Stop and Wait Mode Disable Function . . . 122
6.9. Resets  . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Part 7: Security Features . . . . . . . . . . . . . .123
7.1. Operation with Security Enabled  . . . . . . . 123
7.2. Flash Access Blocking Mechanisms  . . . . 124
Part 8: General Purpose Input/Output 
(GPIO) . . . . . . . . . . . . . . . . . . . . . . . 126
8.1. Introduction  . . . . . . . . . . . . . . . . . . . . . . . .126
8.2. Memory Maps  . . . . . . . . . . . . . . . . . . . . . .127
8.3. Configuration  . . . . . . . . . . . . . . . . . . . . . . .127
Part 9: Joint Test Action Group (JTAG)  . 132
9.1. JTAG Information . . . . . . . . . . . . . . . . . . . .132
Part 10: Specifications  . . . . . . . . . . . . . . . 132
10.1. General Characteristics  . . . . . . . . . . . . . .132
10.2. DC Electrical Characteristics  . . . . . . . . . .136
10.3. AC Electrical Characteristics  . . . . . . . . . .140
10.4. Flash Memory Characteristics  . . . . . . . . .140
10.5. External Clock Operation Timing . . . . . . .141
10.6. Phase Locked Loop Timing  . . . . . . . . . . .141
10.7. Crystal Oscillator Timing  . . . . . . . . . . . . .142
10.8. External Memory Interface Timing . . . . . .142
10.9. Reset, Stop, Wait, Mode Select, and 
Interrupt Timing . . . . . . . . . . . . . .145
10.10. Serial Peripheral Interface (SPI) Timing .147
10.11. Quad Timer Timing  . . . . . . . . . . . . . . . .151
10.12. Quadrature Decoder Timing . . . . . . . . . .151
10.13. Serial Communication Interface (SCI) 
Timing  . . . . . . . . . . . . . . . . . . . . .152
10.14. Controller Area Network (CAN) Timing  .153
10.15. JTAG Timing  . . . . . . . . . . . . . . . . . . . . .153
10.16. Analog-to-Digital Converter (ADC) 
Parameters  . . . . . . . . . . . . . . . . .155
10.17. Equivalent Circuit for ADC Inputs . . . . . .158
10.18. Power Consumption . . . . . . . . . . . . . . . .158
Part 11: Packaging  . . . . . . . . . . . . . . . . . . 160
11.1. 56F8357 Package and Pin-Out 
Information . . . . . . . . . . . . . . . . . .160
11.2. 56F8157 Package and Pin-Out 
Information . . . . . . . . . . . . . . . . . .163
Part 12: Design Considerations . . . . . . . . 167
12.1. Thermal Design Considerations . . . . . . . .167
12.2. Electrical Design Considerations . . . . . . .168
12.3. Power Distribution and I/O Ring 
Implementation  . . . . . . . . . . . . . .169
Part 13: Ordering Information  . . . . . . . . . 170
Table of Contents