參數資料
型號: MC56F8157
廠商: Electronic Theatre Controls, Inc.
英文描述: 16-BIT HYBRID CONTROLLERS
中文描述: 16位混合控制器
文件頁數: 145/172頁
文件大?。?/td> 2444K
代理商: MC56F8157
Reset, Stop, Wait, Mode Select, and Interrupt Timing
56F8357 Technical Data, Rev. 8.0
Freescale Semiconductor
Preliminary
145
10.9 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 10-17 Reset, Stop, Wait, Mode Select, and Interrupt Timing
1,2
1. In the formulas, T = clock cycle. For an operating frequency of 60MHz, T = 16.67ns. At 8MHz (used during Reset and
Stop modes), T = 125ns.
2. Parameters listed are guaranteed by design.
3. During Power-On Reset, it is possible to use the device’s internal reset stretching circuitry to extend this period to 2
21
T.
4. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state.
This is not the minimum required so that the IRQA interrupt is accepted.
5. The interrupt instruction fetch is visible on the pins only in Mode 3.
Characteristic
Symbol
Typical
Min
Typical
Max
Unit
See Figure
RESET Assertion to Address, Data and
Control Signals High Impedance
t
RAZ
21
ns
10-5
Minimum RESET Assertion Duration
t
RA
16T
ns
10-5
RESET Deassertion to First External Address
Output
3
t
RDA
63T
64T
ns
10-5
Edge-sensitive Interrupt Request Width
t
IRW
1.5T
ns
10-6
IRQA, IRQB Assertion to External Data
Memory Access Out Valid, caused by first
instruction execution in the interrupt service
routine
t
IDM
18
ns
10-7
t
IDM
- FAST
14
IRQA, IRQB Assertion to General Purpose
Output Valid, caused by first instruction
execution in the interrupt service routine
t
IG
18
ns
10-7
t
IG
- FAST
14
Delay from IRQA Assertion (exiting Wait) tto
External Data Memory Access
4
t
IRI
22
ns
10-8
t
IRI
-FAST
18
Delay from IRQA Assertion to External Data
Memory Access (exiting Stop)
t
IF
ns
10-9
t
IF
- FAST
IRQA Width Assertion to Recover from Stop
State
5
t
IW
1.5T
ns
10-9
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