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參數(shù)資料
| 型號： | MC33410FTA |
| 廠商： | MOTOROLA INC |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | DUAL CVSD/PLL CORDLESS PHONE SYSTEM |
| 中文描述： | TELECOM, CORDLESS, SUPPORT CIRCUIT, PQFP48 |
| 封裝： | PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 9/20頁 |
| 文件大小： | 300K |
| 代理商： | MC33410FTA |
MC33410
9
MOTOROLA RF/IF DEVICE DATA
a typical application the Transmit PLL section will be set up to
generate the transmit frequency, and the Receive PLL
section will be set up to generate the LO1 frequency. The two
sections are identical, and function independently. External
requirements for each include a low pass filter, a 900 MHz
VCO, and a 64/65 or 128/129 dual modulus prescaler.
The frequency output of the VCO is to be reduced by the
dual modulus prescaler, and then input to the MC33410 (at
Pin 2 or 8). That frequency is then further reduced by the
programmable 13–bit counter (bits 1/19–7 or 2/19–7), and
provided to one side of the Phase Detector, where it is
compared with the PLL reference frequency. The output of
the phase detector (at Pin 4 or 6) is a bi–directional charge
pump which drives the VCO through the low pass filter. Bits
1/20 and 2/20 set the gain of each of the two charge pumps
to either 100/2
π
μ
A/Radian or 400/2
π
μ
A/Radian. The polarity
of the two phase detector outputs is set with bits 7/22 and
7/23. If the bit=0, the appropriate PLL is configured to operate
with a non–inverting low pass filter/VCO combination. If the
low pass filter/VCO combination is inverting, the polarity bit
should be set to 1.
The 7–bit A and A’ counters (bits 1/6–0 and 2/6–0) are to
be set to drive the Modulus Control input of the 64/65 or
128/129 dual modulus prescalers. The Modulus Control
outputs (Pins 1 and 9) can be set to either a voltage mode or
a current mode with bit 7/13.
To calculate the settings of the N and A registers, the
following procedure is used:
fVCO
fPLL
Nt (Nt must be an integer)
Nt
P
N
Equation 1
Equation 2
A = Remainder of Equation 2
(decimal part of N x P)
where:
fVCO = the VCO frequency
fPLL = the PLL Reference Frequency set within
the MC33410
P = the smaller divisor of the dual modulus
prescaler (64 for a 64/65 prescaler)
N = the whole number portion is the setting for the
N (or N’) counter within the MC33410
A = the setting for the A (or A’) counter within the
MC33410
For example, if the VCO is to provide 910 MHz, and the
internal PLL reference frequency is 50 kHz, then the
equations yield:
910 x 106
50 x 103
Equation 3
Nt
18,200
N
18,200
64
284.375
A
0.375 x 64
24
The N register setting is 284d (0 0001 0001 1100), and the
A register setting is 24d (001 1000).
2nd LO (LO2)
This PLL is designed to be the 2nd Local Oscillator in a
typical 900 MHz system, and is designed for frequencies up
to 80 MHz. The VCO and varactor diodes are included, and
are to be used with an external tank circuit (Pins 43 to 45).
Bits 7/20–18 are used to select an internal capacitor, with
a value in the range of 0 to 7.6 pF, to parallel the varactor
diodes and the tank’s external capacitor. This permits a
certain amount of fine tuning of the oscillator’s performance.
See Table 9.
A buffered output is provided to drive, e.g., a mixer. The
frequency is set with the programmable 14–bit counter (bits
3/13–0) in conjunction with the PLL reference frequency. For
example, if the reference frequency is 50 kHz, and the 2nd
LO frequency is to be 63.3 MHz, the 14–bit counter needs to
be set to 1266d (00 0100 1111 0010). The output level is
dependent on the value of the impedance at Pin 41, partly
determined by the external pullup resistor.
The output of the phase detector is a bi–directional charge
pump which drives the varactor diodes through an external
low pass filter. Bit 3/14 sets the gain of the charge pump to
either 100/2
π
μ
A/Radian or 400/2
π
μ
A/Radian. Bit 7/21 sets
its polarity – if 0, the PLL is configured to operate with a
non–inverting low pass filter/VCO combination. If the low
pass filter/VCO combination is inverting, the polarity bit
áááááááááááááááá
áááááááááááááá
áááááááá
Bits 20–18
ááááá
0 pF
Capacitor
Capacitor
Bits 20–18
ááááá
4.3 pF
Capacitor
Capacitor
ááááá
000
100
001
1.1 pF
101
5.4 pF
010
2.2 pF
110
6.5 pF
011
3.3 pF
111
7.6 pF
VB Reference Voltage
The VB voltage (
≈
1.5 V) is available at Pin 33. It will have
a production tolerance of
±
6%, and can be adjusted over a
±
9% range using bits 3/20–17. The adjustment steps will be
≈
1.2% each. VB can be used to bias external circuitry, as
long as the load current on this pin does not exceed 10
μ
A.
Low Battery/Carrier Detect
This circuit will provide an indication of either Low Battery
voltage, or a low carrier signal applied to Pin 36 (MP1) from
an RSSI circuit. The desired mode is selected with bit 6/5.
A) Low Battery Mode (Bit 6/5 = 0)
The supply voltage at Pin 18 is applied to the comparator
through an internal resistor divider, and is compared to the
internal reference VB (
≈
1.5 V). The comparator has
≈
15 mV
of hysteresis, measured at VCC. The resistor divider is
adjustable using bits 3/23–21. The Low Battery threshold
voltage will then be equal to the VB voltage multiplied by the
factor listed in Table 10. For example, if VB = 1.5 V, and bits
3/23–21 = 011, the threshold will be 3.21 V.
B) Carrier Detect Mode (Bit 6/5 = 1)
Pin 36 (MP1) must be set to the Hi–Z/CD Input mode by
setting bits 7/5–4 to 11. MP1 will then be an input with an
input impedance of
≈
600 k
, referenced to VB. An analog
signal applied to MP1 will be applied to the comparator
through an internal adjustable gain stage (adjustable using
bits 3/23–21), and is compared to the internal reference VB.
The comparator has
≈
18.0 mV of hysteresis, measured at
Pin 36. The threshold voltage will then be equal to the VB
voltage multiplied by the factor listed in Table 10. For
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