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參數(shù)資料
| 型號： | MC33410FTA |
| 廠商： | MOTOROLA INC |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | DUAL CVSD/PLL CORDLESS PHONE SYSTEM |
| 中文描述： | TELECOM, CORDLESS, SUPPORT CIRCUIT, PQFP48 |
| 封裝： | PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 300K |
| 代理商： | MC33410FTA |
MC33410
12
MOTOROLA RF/IF DEVICE DATA
Figure 5. Entering/Exiting Data Modem Mode
Clock
Data
Enable
Address 1011
Recovered Clock Output @ Pin 12
Sets Data Pin
to Output
Sets Data Pin
to Input
After address 11 is clocked in, the Enable falling edge will
cause Pin 12 (Data) to switch to an output, providing the
recovered clock. The microprocessor’s data pin must be
changed to an input prior to this falling edge. This sequence
is effective only if bit 5/20 is set to a 1.
During the time that recovered clock is available at Pin 12,
the microprocessor port is unavailable for any control
functions.
To exit the Data Modem mode, the Enable line is to be
taken high and low (the clock is to be stable during this active
high pulse). The falling edge will set Pin 12 to be an input,
allowing normal use of the microprocessor port. The next
step is to set bit 5/20 to a 0. Other register bits can then be set
as needed.
To prevent inadvertent incorrect operation of the
microprocessor port, bit 5/20 must always be set to 0 when
the Data Modem mode is not in use.
Power Supply/Power Saving Modes
The power supply voltage, applied to all VCC pins, can
range from 2.7 to 5.5 V. All VCC pins must be within
±
0.5 V of
each other, and each must be bypassed. It is recommended
a ground plane be used, and all leads to the MC33410 be as
short and direct as possible. The supply and ground pins are
distributed as follows:
1. Pins 18, 27 and 37 are internally connected together, and
provide power to the audio amplifiers, filters, CVSD
encoder and decoder, and the low frequency (CVSD rate)
logic circuits. Pins 21, 30 and 40 are the ground pins for
these sections.
2. Pin 3 provides power to the Rx PLL section. Pin 5 is the
ground pin.
3. Pin 7 provides power to the Tx PLL section, and the MPU
interface. Pin 5 is the ground pin.
4. Pin 42 provides power to the 2nd LO section. Pins 46 and
48 are the ground pins.
To conserve power, various sections can be individually
disabled, using bits 5/10–0 (setting a bit to 1 disables the
section).
1. Reference Oscillator Disable (bit 5/0) – The reference
oscillator at Pins 14 and 15 is disabled, thereby denying a
clock to the three PLLs, the CVSD Encoder, and the
switched capacitor filters.
2. Tx PLL Disable (bit 5/1) – The 13–bit and 7–bit counters,
input buffer, phase detector, and modulus control blocks
are disabled. The charge pump output at Pin 6 will be in a
Hi–Z state.
3. Rx PLL Disable (bit 5/2) – The 13–bit and 7–bit counters,
input buffer, phase detector, and modulus control blocks
are disabled. The charge pump output at Pin 4 will be in a
Hi–Z state.
4. LO2 PLL Disable (bit 5/3) – The VCO, 14–bit counter,
output buffer, and phase detector are disabled. The
charge pump output at Pin 47 will be in a Hi–Z state.
5. Rx Data Path Disable (bit 5/4) – The data slicer, clock
recovery block, descrambler, data detect register, and the
status output circuit are disabled. The state of the status
line (Pin 13 and bit 5/22) will not change upon disabling this
section.
6. CVSD Decoder Disable (bit 5/5) – The CVSD Decoder and
the Rx 1010 Generator are disabled.
7. Rx Audio Path Disable (bit 5/6) – The anti–aliasing filter,
low pass filter, and variable gain stage are disabled.
8. Power Amplifier Disable (bit 5/7) – The two power
amplifiers are disabled. Their outputs will go to a Hi–Z
state.
9. Tx Audio Path Disable (bit 5/8) – Disables the microphone
amplifier, low pass filter, and smoothing filter.
10. CVSD Encoder Disable (bit 5/9) – The CVSD Encoder, Idle
Channel detect circuit, the Tx 1010 Generator, the Tx Data
register, and the scrambler are disabled.
11. Low Battery/Carrier Detect Disable (bit 5/10) – The LB/CD
circuit is disabled. The output, at bit 5/23 and Pin 16 will be
at a logic high.
12. Idle Channel Detect Disable (bit 5/18) – Powers down the
Idle Channel Detect circuit.
Note: The 12–bit reference counter is disabled if the three
PLLs are disabled (bits 5/1–3 = 1).
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