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參數(shù)資料
| 型號(hào)： | MC33410FTA |
| 廠商： | MOTOROLA INC |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | DUAL CVSD/PLL CORDLESS PHONE SYSTEM |
| 中文描述： | TELECOM, CORDLESS, SUPPORT CIRCUIT, PQFP48 |
| 封裝： | PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 300K |
| 代理商： | MC33410FTA |
MC33410
7
MOTOROLA RF/IF DEVICE DATA
d. Upon loading register 9, the MC33410 automatically sends
out (at Pin 17) the code word, followed by the data word,
at the CVSD clock rate.
When the data word is completely sent out, the MC33410
will then return Pin 17 to its previous source of digital
information (CVSD Encoder or Tx 1010 Generator).
Scrambler/Digital Output
The scrambler receives digital data from the CVSD
Encoder, or the Tx 1010 Generator, or the Tx Data Register,
to be output at Pin 17. The output level is 0 to VCC. The
scrambler can be bypassed with Bit 7/1.
The scrambler, better known as a randomizer, provides
not only a level of communication security, but also helps
ensure the digital output will not contain an abnormally long
string of 1s or 0s which can adversely affect the CVSD
Decoder operation, as well as the RF section. The scrambler
is a maximal–length shift register sequence generator. The
length of the shift register is selectable to one of eight values
with bits 7/10–8 (the descrambler in the receiving unit must
be set the same). Table 5 lists the polynomial associated with
each tap selection.
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No.
Bit 10
Bit 9
Bit 8
Shif R
Shift Register Length
P l
Polynomial
1 + z–1 + z–2
1 + z–2 + z–3
1 + z–3 + z–4
1 + z–3 + z–5
1 + z–5 + z–6
1 + z–6 + z–7
1 + z–5 + z–9
1 + z–7 + z–10
i l
0
0
0
0
2
1
0
0
1
3
2
0
1
0
4
3
0
1
1
5
4
1
0
0
6
5
1
0
1
7
6
1
1
0
9
7
1
1
1
10
Data Slicer/Clock Recovery
The data slicer will receive the low level digital signal from
the RF receiver section at Pin 38. The input signal to the data
slicer must be >200 mVpp. Hysteresis of 50 mV is internally
provided. The output of the data slicer will be same
waveform, but with an amplitude of 0 to VCC, and can be
observed at Pin 36 (MP1) if bits 7/5–4 are set to 10. The
output can be inverted by setting bit 5/19 = 1.
The clock recovery block will generate a phase locked
clock, equal to the CVSD data rate, from the incoming data,
as long as the Encoder Counter (bits 4/23–18) is set for that
data rate. The recovered clock can be observed at Pin 39
(MP2) if bits 7/7–6 are set to 00. The data from the clock
recovery block can be observed at Pin 36 if bits 7/5–4 are set
to 00. The clock recovery block may be bypassed by setting
bit 7/0 to 1. With this setting the data slicer output will go
directly to the descrambler, and the encoder clock will
replace the Clock Recovery Clock.
Tables 6 and 7 summarize the options available at MP1
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Bit 5
Bit 4
Function
0
0
Data from clock recovery block
0
1
Data Detect Output
1
0
Data Slicer Output
1
1
Hi–Z/ CD Input
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Register 7
0
0
Output recovered clock
0
1
Input CVSD Decoder clock
1
X
Disabled (Hi–Z)
When MP1 is set to a Hi–Z condition, the pin is an input for
the CD (Carrier Detect) function, with an input impedance of
600 K
. See the section entitled Low Battery/Carrier Detect
for an explanation of this function.
Descrambler
The descrambler receives the scrambled data from the
clock recovery block (or the data slicer if bit 7/0 = 1), and
descrambles it to the original data as long as the selected
taps are the same as those in the transmitting scrambler (see
Table 5). The descrambler block is the same configuration as
the scrambler, and is self–synchronizing. The descrambler
can be bypassed with bit 7/1.
Data Detect Register/Status Output/Rx Data Register
The Data Detect register will continuously compare the
descrambled data it receives with the 16 or 24–bit code word
stored in the Tx Data Register (loaded through register 8).
Upon detecting a match, and after the code word passes
through the shift register, the following (16 or 24–bit) data
word will be stored into the Rx Data Register, and then loaded
into register 10 of the MPU Interface. At this time the Status
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