參數(shù)資料
型號(hào)： MC33410FTA
廠商： MOTOROLA INC
元件分類： 無繩電話/電話
英文描述： DUAL CVSD/PLL CORDLESS PHONE SYSTEM
中文描述： TELECOM, CORDLESS, SUPPORT CIRCUIT, PQFP48
封裝： PLASTIC, LQFP-48
文件頁數(shù)： 15/20頁
文件大?。?/td> 300K
代理商： MC33410FTA
MC33410
15
MOTOROLA RF/IF DEVICE DATA
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6 – 0
1000000
Sets the 7–bit Tx A counter for the Tx PLL.
1
19 – 7
10....0
Sets the 13–bit Tx N counter for the Tx PLL.
2
6 – 0
1000000
Sets the 7–bit Rx A’ counter for the Rx PLL.
2
19 – 7
10....0
Sets the 13–bit Rx N’ counter for the Rx PLL.
3
13 – 0
10....0
Sets the 14–bit counter for the 2nd LO.
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Power Up
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4
11 – 0
$800
Sets the 12–bit counter for the PLL Reference Clock.
7
13
0
Sets the FTx MC and FRx MC output level to be from ground to VCC. If this bit is 0, the
output level is
±
100
μ
A.
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1
20
0
Sets the Tx phase detector charge pump output current. 0 =
±
100
μ
A,
and 1 =
±
400
μ
A.
Register
Bit No.
Default
Function
(when bit = 1 if appropriate)
2
20
0
Sets the Rx phase detector charge pump output current. 0 =
±
100
μ
A,
and 1 =
±
400
μ
A.
3
14
0
Sets the LO2 phase detector charge pump output current. 0 =
±
100
μ
A,
and 1 =
±
400
μ
A.
7
20 – 18
000
Selects the value of the internal capacitor between Pins 43 to 45, to fine tune the LO2
tank circuit. See Table 9.
7
21
0
Sets the polarity of the 2nd LO phase detector charge pump output for an inverting low
pass filter/VCO combination.
7
22
0
Sets the polarity of the Rx phase detector charge pump output for an inverting low
pass filter/VCO combination.
7
23
0
Sets the polarity of the Tx phase detector charge pump output for an inverting low pass
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22, 21
00
Sets CVSD Decoder minimum step size per Table 3.
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Default
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Power Up
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2
22, 21
00
Sets CVSD Encoder minimum step size per Table 3.
3
16 – 15
11
Set the CVSD encoder/decoder for the selected clock rate. (Table 2)
4
23 – 18
100000
Sets the 6–bit counter to set the CVSD Encoder clock rate.
6
3
0
Selects the Rx 1010 Generator to the CVSD decoder.
Selects the Tx 1010 Generator to the scrambler.
Disables the CVSD charge compensation circuit, which affects idle channel
performance.
6
4
0
7
14
0
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5
14 – 11
0111
Sets the 4–bit idle channel counter to set the response delay for the idle channel
detect circuit.
Idle Channel Detector
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Register
Bit No.
Power Up
Default
Function
(when bit = 1 if appropriate)
5
17 – 15
100
Sets the idle channel detect threshold level. See Table 4.
5
21
N/A
Indicates an idle channel condition has been detected (Output). This output is
unaffected by bit 7/2.
7
2
0
Disables the automatic idle channel detect at the CVSD encoder. Bit 5/21 is still active.
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