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參數(shù)資料
| 型號： | MC33410FTA |
| 廠商： | MOTOROLA INC |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | DUAL CVSD/PLL CORDLESS PHONE SYSTEM |
| 中文描述： | TELECOM, CORDLESS, SUPPORT CIRCUIT, PQFP48 |
| 封裝： | PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 300K |
| 代理商： | MC33410FTA |
MC33410
6
MOTOROLA RF/IF DEVICE DATA
FUNCTIONAL DESCRIPTION
Note: In the following descriptions, control bits in the MPU
Serial Interface for the various functions will be identified by
register number and bit number. For example, bit 3/19
indicates bit 19 of register 3. Bits 5/14–11 indicates register 5,
bits 14 through 11. Please refer to Figure 1.
Transmit Speech Processing Section
This section is made up of the externally adjustable
microphone amplifier (Pins 22 to 23), internally adjustable
gain stage, two low pass filters, and a mute switch.
The gain of the microphone amplifier is set with external
resistors to receive the audio from the microphone (in the
handset), or from the hybrid (in the base unit), or from any
other audio source. The MCO output has rail–to–rail
capability, and the dc bias level is at VB (
≈
1.5 V).
The adjustable gain stage, referred to as the Remote
Gain Adjust, provides 5 levels of gain in 4.0 dB increments.
It is controlled with bits 6/15–11 as shown in Table 1.
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00001
–8.0 dB
00010
–4.0 dB
00100
0 dB
01000
+4.0 dB
10000
+8.0 dB
Other combinations for the 5 bits are invalid.
The Low Pass Filter after the gain stage is a switched
capacitor filter with a corner frequency at 5.0 kHz. The
subsequent smoothing low pass filter has a corner frequency
at 30 kHz, and is designed to filter out high frequency clock
noise from the previously mentioned switched capacitor filter.
The mute switch at Pin 20 will mute a minimum of 60 dB.
Bit 6/2 controls the mute.
CVSD Encoder/Idle Channel/Tx Data Register
The analog signals to be digitized are input at Pin 19 to the
CVSD Encoder. The output of the encoder will be the digital
equivalent of the audio, at the selected clock rate. Based on
the reference frequency, bits 4/23–18 are used to set the 6 Bit
Encoder Counter, in conjunction with the subsequent
÷
16
divider, to set the CVSD Encoder frequency to 32, 50, or
64 kHz. Bits 3/16–15 will set the CVSD for proper operation
at the selected frequency, according to Table 2.
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Bit 16
Bit 15
Table 2. CVSD Clock/Data Rates
Register 3
Clock/Data Rate
0
1
32 kHz
1
0
50 kHz
1
1
64 kHz
The Encoder’s minimum step size can be selected using
bits 2/22–21, according to Table 3.
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Encoder
Register 2
Bits 22, 21
Bits 22, 21
Decoder
Register 1
Step Size
00
00
No minimum
01
01
1.4 mV
10
10
5.6 mV
11
11
22.4 mV
The Tx 1010 Generator, when selected, provides an
alternating “1–0” pattern (a square wave at half the CVSD
clock rate) to the scrambler. This represents the lowest
amplitude analog signal, and can be used when it is desired
to send a quiet signal. Selection of this block can occur either
automatically, or intentionally, as follows:
a. The automatic selection occurs when the Idle Channel
Detector senses the average audio signal at Pin 19 is
below a threshold which is set with bits 5/17–15 (See
Table 4). Bits 5/14–11 select a time delay for the automatic
threshold detection to occur. The minimum delay is zero,
with these bits set to 0000. Changing the bits provides
delay in increments of 32 clock cycles (of the CVSD
Encoder clock). The maximum delay is 480 clock cycles,
(7.5 mS at 64 kHz). When the average audio signal at
Pin 19 increases above the threshold, the Tx 1010
Generator will be deselected with no delay. This automatic
switchover feature can be disabled with bit 7/2. Bit 5/21
indicates when an idle channel condition has been
detected. This output bit will be functional even when the
idle channel detector is disabled with bit 7/2. Bit 5/18 will
power down the Idle Channel Detect Circuit as a power
saving measure.
b. Bit 6/4 can be used to intentionally select the Tx 1010
Generator at any time.
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Threshold
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Register 5
Register 5
000
–50 dBV
100
–60 dBV
001
–52.5
101
–62.5
010
–55
110
–65
011
–57.5
111
–67.5
The Tx Data Register is used for the transmission of data
between the handset and base units. The procedure is as
follows:
a. At the receiving unit: The code word (16 or 24 bits, set with
bit 7/11) identifying that a data transmission is occurring
must be loaded into the Tx Data Register (by loading
register 8). This is used to detect when a code word is sent
from the transmitting unit.
b. At the transmitting unit: The same code word as above is
loaded into register 8. It is automatically loaded into the Tx
Data Register.
c. The data word (16 or 24 bits, set with bit 7/12) is then loaded
into register 9.
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