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參數(shù)資料
| 型號： | MC33410FTA |
| 廠商： | MOTOROLA INC |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | DUAL CVSD/PLL CORDLESS PHONE SYSTEM |
| 中文描述： | TELECOM, CORDLESS, SUPPORT CIRCUIT, PQFP48 |
| 封裝： | PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 11/20頁 |
| 文件大?。?/td> | 300K |
| 代理商： | MC33410FTA |
MC33410
11
MOTOROLA RF/IF DEVICE DATA
b) Read Operation:
To read the output bits (bits 5/23–21, or all of register 10),
or the contents of any register, the following sequence is
required (see Figure 3):
1. The Enable line is taken high.
2. Five bits are entered:
– The first bit must be a 1 to indicate a Read operation.
– The next four bits identify the register address
(0001–1010). The MSB is entered first.
3. After the 5th clock is taken low, the Enable line is taken low.
At this transition, the address is latched in and decoded,
and the contents of the selected register is loaded into the
24–bit output shift register. At this point, the Data line
(Pin 12) is still an input.
4. While maintaining the Enable line low, the data is read out.
The first clock rising edge will change the Data line to an
output, and the MSB will be present on this line.
5. The full contents of the register are then read out (MSB first,
LSB last) with a total of 24 clock rising edges, including the
one in step 4 above. It is recommended that the MPU read
the bits at the clock’s falling edge. If only bit 23, 22, or 21
of register 5 are to be read, this can be done with one, two,
or three clock rising edges, respectively.
6. After the last clock pulse, the Enable line is to be taken high
and then low. The falling edge of this pulse returns the Data
pin to be an input. The clock line can be at a logic high or
low, but must not transition in either direction during this
Enable pulse.
7. The Enable line must then be kept low until the next
communication.
Data Modem Mode
For applications where the MC33410 is to be used in a
900 MHz wireless system for transmitting data only
(non–voice), a mode can be set which bypasses the speech
digitizing sections. The resulting configuration makes use of
those sections associated with data only, i.e., the scrambler,
descrambler, and clock recovery section. Also functional are
the three PLLs, the audio receive path (Pins 34 to 28), the
transmit audio path (Pins 23 to 20), and the Low Battery
circuit (but not the Carrier Detect mode).
In this mode, the MC33410 will provide the transmit data
clock from the crystal, in conjunction with the internal 6–bit
counter (bits 4/23–18) and the
÷
16 block associated with that
counter. The transmit data clock is available at Pin 13, and
can be used to synchronize the external data source. The Tx
data is input at Pin 39, passes through the scrambler, and
outputs at Pin 17.
The demodulated data from the RF receiver is input at
Pin 38, and is applied to the data slicer, and the clock
recovery block. The recovered clock is output at Pin 12. The
data passes through the descrambler, and is output at Pin 36.
Figure 4 is a diagram of the data paths through the
MC33410.
The procedure for entering the Data Modem mode is in
Table 11:
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Tx Clk = Fcrystal/(16 x Counter).
Function
4/23 – 18
Bits
As
Desired
Bit Value
Set Scrambler & Descrambler tap
setting (Bit 7/1 = 0).
7/10 – 8
As
Desired
Bypass Data Detect.
7/3
1
Set MP1 to Data Detect Output.
7/5 – 4
01
Set Test Mode bits to connect Encode
Clock to Status (Pin 13).
7/17 – 15
110
Set Data Modem Mode (MP2 to
scrambler Input).
5/20
1
Write to Register 11 as shown in
Figure 5 to configure Pin 12.
N/A
N/A
The above sequence is not critical, except that the last two
steps must be the setting of bit 5/20, and writing to register
11. Writing to register 11 is shown in Figure 5.
Figure 4. Data Modem Mode Configuration
Tx Data
Input
Scrambler
Prog. 6–bit
Counter
39
14
15
38
Clock
Recovery
17
13
36
12
Descrambler
÷
16
Rx Data
Input
Crystal
Recovered
Rx Clock
Rx Data
Out
Tx Clock
Out
Tx Data
Out
MC33410
Data
Slicer
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