參數(shù)資料
型號(hào)： MC33410FTA
廠商： MOTOROLA INC
元件分類： 無(wú)繩電話/電話
英文描述： DUAL CVSD/PLL CORDLESS PHONE SYSTEM
中文描述： TELECOM, CORDLESS, SUPPORT CIRCUIT, PQFP48
封裝： PLASTIC, LQFP-48
文件頁(yè)數(shù)： 8/20頁(yè)
文件大?。?/td> 300K
代理商： MC33410FTA
MC33410
8
MOTOROLA RF/IF DEVICE DATA
output at Pin 13, and bit 5/22, will go high. The external
microprocessor can then retrieve the data word by reading
register 10, at which time the Status pin and bit will go low.
Upon detection of a code word as described above, the
CVSD Decoder will be provided with 32, 40, or 48–bits of a
1010 pattern (idle channel) to minimize disturbances to the
audio. After the data word is loaded into register 10, the
CVSD Decoder resumes receiving data from the
descrambler. The audio is therefore interrupted with a low
level signal for a maximum of 48 clock cycles (0.75 mSec at
64 kHz).
The Data Detect register can be bypassed by setting bit
7/3 = 1.
CVSD Decoder/Decoder Clock/Idle Channel
The CVSD Decoder will provide the analog equivalent, at
Pin 35, of the digital data it receives from the descrambler, or
from the 1010 generator (idle channel generator). There is a
single pole filter at the Decoder output to reduce the clock
noise normally present on a CVSD analog output. The CVSD
Decoder is self synchronizing as long as the decoder clock
matches the data rate, and the Decoder has been set with
bits 3/16–15 according to Table 2.
The Decoder clock is provided from the Clock Recovery
block by setting bits 7/7–6 to 00 or 1X. The clock is internally
provided to the Decoder, and is available at Pin 39.
Alternately, a Decoder clock can be provided from an
external source to Pin 39 by setting bit 7/7–6 to 01 (see
Table 7).
The Rx 1010 Generator provides an alternating 1–0
pattern (a square wave at half the CVSD clock rate) to the
CVSD Decoder, resulting in the lowest amplitude analog
signal at Pin 35. The 1010 Generator is automatically
selected whenever data is detected and received by the Data
Detection Circuit, as described above. Additionally, the 1010
Generator can be selected with bit 6/3 at any time.
The Decoder’s minimum step size can be selected using
bits 1/22–21, according to Table 3.
Receive Audio Path
The Receive Audio Path (Pins 34 to 32) consists of an
anti–aliasing filter, a low pass filter, a gain adjust stage, and a
mute switch.
Since the analog output of the CVSD Decoder (typically
input at Pin 34) will contain noise at the CVSD clock rate, the
anti–aliasing filter, with a corner frequency at 30 kHz, is
provided to prevent aliasing of that clock noise with the
subsequent switched capacitor filter.
The switched capacitor low pass filter is a 3 pole filter, with
a corner frequency at 5.0 kHz. This is designed to remove the
clock noise from the CVSD Decoder output signal, as well as
provide bandwidth limiting in the audio range.
The gain stage provides 28.5 dB of gain adjustment in 19
steps (1.5 dB each), measured from Pin 34 to 32. Bits 6/10–6
are used to set the gain according to Table 8.
The mute switch at Pin 32, controlled by bit 6/1, will mute
a minimum of 60 dB.
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Bits 10...6
Gain
Bits 10...6
Gain
00110
–13.5 dB
10000
+1.5 dB
00111
–12.0 dB
10001
+3.0 dB
01000
–10.5 dB
10010
+4.5 dB
01001
–9.0 dB
10011
+6.0 dB
01010
–7.5 dB
10100
+7.5 dB
01011
–6.0 dB
10101
+9.0 dB
01100
–4.5 dB
10110
+10.5 dB
01101
–3.0 dB
10111
+12.0 dB
01110
–1.5 dB
11000
+13.5 dB
01111
0.0 dB
11001
+15.0 dB
Power Amplifiers
The power amplifiers (Pins 28, 29, 31) are designed to
drive the earpiece in a handset, or the telephone line via a
hybrid circuit in the base unit. Each output (PAO+ and PAO–)
can source and sink 5 mA, and can swing 2.0 Vpp each. The
gain of the amplifiers is set with a feedback resistor from Pin
29 to 31, and an input resistor at Pin 31. The differential gain
is 2x the resistor ratio. Capacitors can be used for frequency
shaping. The pins’ dc level is VB (
≈
1.5 V).
The Mute switch, controlled with bit 6/0, will provide 90 dB
of muting with a 50 k
feedback resistor. The amount of
muting will depend on the value of the feedback resistor.
Reference Clock
The reference clock provides the frequency basis for the
three PLLs, the switched capacitor filters, and the CVSD
Encoder section. The source for the reference clock can be a
crystal in the range of 4.0 to 18.25 MHz connected to Pins 14
& 15, or it can be an external source connected to Fref In (Pin
14). The reference frequency is directed to:
a. A programmable 12–bit counter to provide the reference
frequency for the three PLLs. The 12–bit counter is to be
set such that, in conjunction with the programmable
counters within each PLL, the proper frequencies can be
produced by each VCO.
b. A programmable 6–bit counter, followed by a
÷
2 stage, to
set the frequency for the switched capacitor filters to
256 kHz, or as close to that as possible.
c. A programmable 6–bit counter which provides the 16x
clock for the Clock Recovery block. This is followed by a
÷
16 stage which provides the CVSD Encoder clock. This
is followed by a
÷
32 stage, and a programmable 4–bit
counter which sets the delay for the Idle Channel Detect
circuit.
Transmit and Receive (LO1) PLL Sections
The transmit and receive PLLs (Pins 6 to 9 and 1 to 4,
respectively) are designed to be part of a 900 MHz system. In
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