參數(shù)資料
型號(hào): MC145572APB
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 9/52頁(yè)
文件大?。?/td> 0K
描述: IC ISDN INTERFACE TXCVER 44-LQFP
標(biāo)準(zhǔn)包裝: 160
類(lèi)型: 收發(fā)器
規(guī)程: RS232
電源電壓: 5V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 44-LQFP
供應(yīng)商設(shè)備封裝: 44-LQFP(10x10)
包裝: 托盤(pán)
MC145572EVK
18
2.5
BIT ERROR ANALYZER INTERFACE
The MC145572EVK ISDN U-Interface Evaluation Kit provides TTL-compatible gated clocks for the B1,
B2, and D time slots to allow easy connection to a bit error rate tester. This is accomplished with the use
of glue logic. Access to these gated clock signals is through the 2 x 20 headers (J9 on the LT side and
J22 on the NT1 side). Figure 2-4 details the connections on both of these headers. The clocks are output
in either an 8- or 10-bit boundary mode at the IDL clock speed.
The MC145572EVK is shipped from the factory congured so its gated clock outputs are derived from the
TSEN output, pin 25, gated with the DCL signal from the IDL2 interface. The 2B+D format is the IDL 10-bit
frame. It can be changed to IDL 8-bit frame format by setting BR7(b0) to a 1 in the appropriate U Transceiver.
Figure 2-4. Access to Bit Error Analyzer Interface Through J22 and J9 Headers
1
2
40
39
DREQ
DGRANT
NTSCPENL
STSCPENL
LTSCPENL
SCPCLK
SCPTX
NTIRQL
NTIDLCLK
NTIDLRX
NTIDLTX
NTFSR
NTFSX
IRQLT
NTSFAR
NTSFAX
NTFREF
NTFREFO
NTGTCLK
SCPRX
GND
J22 (NT)
1
2
40
39
LTFREF
EXTREF
LTSCPENL
SCPCLK
SCPTX
LTIRQL
LTIDLCLK
LTIDLRX
LTIDLTX
LTFSR
LTFSX
8 kHz
LTSFAR
LTSFAX
LTFREFO
LTGTCLK
SCPRX
GND
J9 (LT)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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