參數(shù)資料
型號： MC145572APB
廠商： Freescale Semiconductor
文件頁數(shù)： 21/52頁
文件大小： 0K
描述： IC ISDN INTERFACE TXCVER 44-LQFP
標準包裝： 160
類型： 收發(fā)器
規(guī)程： RS232
電源電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 44-LQFP
供應(yīng)商設(shè)備封裝： 44-LQFP（10x10）
包裝： 托盤
29
MC145572EVK
SCPRx: SCP Receive Input (SCP Rx).
SCPRX is used to input control, status, and data information to the two MC145572 U-Interface Transceivers
and the MC145574 S/T-Interface Transceiver.
LTIRQ: Interrupt Request (LT U-Interface Transceiver IRQ).
The LTIRQ pin is an active low open drain output used to signal the MCU devices that an interrupt condition
exists in the LT MC145572 U-Interface Transceiver (U1). On clearing the interrupt condition, the LTIRQ
pin is returned to the high state.
LTIDLCLK: (LT U-Interface Transceiver Pin DCL).
This pin is an input when the MC145572 is in slave mode and an output when the MC145572 is in master
mode, as established by switch S2-2, MAS/SLV. As a timing master in LT mode, this pin provides a 512 kHz,
2.048 MHz, or 2.56 MHz clock frequency. In GCI mode, the 2.56 MHz clock is not available. This choice
is programmed in BR7 or from the CLKSEL pin of the LT side MC145572. In GCI mode S5-4,
GCI2048/GCI512 selects the clock rate on this pin. In slave mode, this pin accepts any clock frequency
from 512 kHz to 8.192 MHz, inclusive.
LTIDLRX: (LT U-Interface Transceiver Pin Din).
This pin is the input for the 2B+D data to be transmitted onto the LT U-Interface. Data bits are input on
sequential falling edges of the LTIDLCLK signal, beginning immediately after the LTFSX pulse occurs. The
LTIDLRX pin is a dont care except during valid B- and D-channel data positions.
LTIDLTX: (LT U-Interface Transceiver Pin Dout).
This pin is the output for the 2B+D data received at the LT U-Interface. Data bits are output on rising edges
of the IDL CLK signal beginning immediately after the LTFSR pulse occurs. The LTIDLTX signal remains
in a high impedance state when not outputting 2B+D data or when a valid FS2 signal is missing.
LTFSR: (LT U-Interface Transceiver Pin FSR).
This pin is an input when the MC145572 is congured for slave mode and an output when congured for
master mode, as established by switch S2-2, MAS/SLV. In the master mode, this output is phase locked
to the 20.480 MHz clock of the LT side U chip. This signal is associated with data output from the Dout pin
of the MC145572.
LTFSX: (LT U-Interface Transceiver Pin FSX).
This pin is an input when the MC145572 is congured for slave mode and an output when congured for
master mode, as established by switch S2-2, MAS/SLV. In the master mode, this output is phase locked
to the signal received at the LT U-Interface. This signal is associated with data input to the Din pin of the
MC145572.
8 kHz: MC145572EVK Reference Clock.
This pin outputs an 8 kHz square wave that is generated by the on-board clock reference. This signal is
available at all times.
LTSFAX: Transmit Superframe Alignment.
This pin carries a signal that indicates the rst 2B+D frame in a U superframe to be transmitted onto the
U-Interface. This signal is not active when the LT side MC145572 is congured for full GCI mode operation.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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