參數(shù)資料
型號(hào)： MC145572APB
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 25/52頁(yè)
文件大?。?/td> 0K
描述： IC ISDN INTERFACE TXCVER 44-LQFP
標(biāo)準(zhǔn)包裝： 160
類(lèi)型： 收發(fā)器
規(guī)程： RS232
電源電壓： 5V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 44-LQFP
供應(yīng)商設(shè)備封裝： 44-LQFP（10x10）
包裝： 托盤(pán)
MC145572EVK
32
2.7.2
NT Side Configuration DIP Switch S4
This DIP switch is used to congure operation of the NT side of the MC145572EVK. In particular, the
MC145572 U-Interface Transceiver is congurable for IDL or GCI operation, master or slave timing mode,
and Parallel or Serial Control Port operation.
2.7.3
LT Side GCI Parameters DIP Switch S1
This DIP switch is used to congure the time slot and input pins of the LT side MC145572 when it is
congured for GCI mode by setting S2-5 to the GCI position. In normal operation, S2-5 is in the IDL2
position and the settings of this DIP switch do not affect operation of the MC145572EVK.
Table 2-7. NT Side Conguration DIP Switch S4
DIP Switch
Function
Description
Factory
Setting
Open
Closed
S4-1
MAS
SLV
Selects the level on the M/S Pin to the NT1 U-Interface Transceiver.
MAS
S4-2
FSR
FSR=FSX
Connects the FSR and FSX pins of the NT side MC145572 when closed. Use only in
slave mode.
FSR
S4-3
8
10
Selects 10- or 8-bit mode gated IDL clock outputs for use with a bit error analyzer on
the NT1 side when the MC145572 is congured for MCU mode operation.
10
S4-4
IDL2
GCI
When open, the MC145572 is congured for MCU operation and the time division
multiplexed bus interface to the MC145572 is in the IDL2 mode. When closed, the
MC145572 is congured for GCI operation and all 2B+D and control/status
information is transferred over the GCI interface.
IDL2
S4-5
PAR
SER
Selects between the serial control port or parallel control port mode of accessing the
NT side MC145572 when S4-4 is in the IDL2 mode position.
SER
S4-6
T_MAS
T_SLV
Selects between setting the MC145574 as a slave or master for the IDL2 bus.
CLKHI
S4-7
RESMCU
Controls the state of the microcontroller reset line. This is an input to the hardware
reset of the MC68HC705C8 and is useful when using another platform to control the
MC145572EVK. When closed, a reset signal is applied to U15.
OPEN
S4-8
FIX
ADP
Selects either the adaptive or the xed timing recovery mode for the S/T-Interface
Transceiver.
ADP
S4-9
TE
NT
Selects the operating mode of the S/T-Interface Transceiver TE mode or NT mode.
This signal is tied to the select lines of an analog multiplexer that congures TE/NT(L)
(U17-4),SG/DGRANT/ANDOUT (U17-8), and DREQUEST/ANDIN (U17-9) on the
MC145574 appropriately.
TE
S4-10
NT1EN
NT1DIS
Turns NT1 function on or off. When the NT1 function is off, the user has complete
control of all maintenance channel registers via the terminal interface. When open,
the NT1 is enabled. When closed, the NT1 is disabled.
NTIDIS
Table 2-8. LT Side GCI Parameters DIP Switch S2
DIP Switch
Function
Description
Factory
Setting
Open
Closed
S1-1
S0HI
S0LOW
Program LT side MC145572 GCI S0 time slot select pin.
S0HI
S1-2
S1HI
S1LOW
Program LT side MC145572 GCI S0 time slot select pin.
S1HI
S1-3
S2HI
S2LOW
Program LT side MC145572 GCI S0 time slot select pin.
S2HI
S1-4
GCI2048
GCI512
Select between 2.048 MHz and 512 kHz DCL clock when LT side MC145572 is in
GCI mode.
GCI2048
S1-5
IN1HI
IN1LOW
Used to select level on IN1 Pin of MC145572 when LT side MC145572 is in GCI
mode.
IN1HI
S1-6
IN2HI
IN2LOW
Used to select level on IN2 Pin of MC145572 when LT side MC145572 is in GCI
mode.
IN2HI
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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