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參數資料
| 型號： | MC145572APB |
| 廠商： | Freescale Semiconductor |
| 文件頁數： | 11/52頁 |
| 文件大小： | 0K |
| 描述： | IC ISDN INTERFACE TXCVER 44-LQFP |
| 標準包裝： | 160 |
| 類型： | 收發(fā)器 |
| 規(guī)程： | RS232 |
| 電源電壓： | 5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LQFP |
| 供應商設備封裝： | 44-LQFP（10x10） |
| 包裝： | 托盤 |
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MC145572EVK
20
2.5.1
Setting Up a Bit Error Rate Test
Bit error rate testing with two different testers has been performed. The Hewlett Packard 1645A Data Error
Analyzer and The Telecommunications Techniques Corporation FIREBERD 6000 with Lab Interface
Adapter have successfully been connected to the MC145572EVK. Any bit error test that accepts TTL level
signals and external data clocks up to 2.56 MHz at TTL levels may be used. The clock interface supports
synchronous clocked data through the use of gated clocks running at IDL rates of 512 kHz, 2.048 MHz,
or 2.56 MHz, as determined by register BR7(b2) and OR7(b4) of the U-Interface Transceiver.
CAUTION
The MC145572EVK does not support EIA-232, RS-422, 50W, or RS-485 interfaces to bit
error rate testers.
To demonstrate the connection of the MC145572EVK U-Interface Transceiver Evaluation Kit to a bit error
rate tester, detailed instructions for one test set-up follows.
EXAMPLE: Executing a 2B+D Loop-Back to the U-Interface at the LT End.
This example shows how to connect a bit error rate tester to the MC145572EVK. Refer to Figure 2-7 for
connection details.
The data ow for this example occurs as follows: data is input to the board by the BERT box on NTRXDATA
at the NT1. This data is then input to the MC145572 where it is framed, coded, and transmitted over the
U-Interface to the LT MC145572, and looped-back internal to the LT MC145572. The data is then
transmitted back to the NT MC145572 over the U-Interface, decoded, deframed, and output from the NT
MC145572 on NTTXDATA to the BERT box where it is compared to the data originally transmitted.
1. Make the following connections to the Bit Error Rate Tester as shown in Figure 2-7.
a. Connect NTTXDATA (BNC J20, Dout pin of the NT U-Interface Transceiver) to the Receive
Data Input of the BERT box.
b. Connect NTRXDATA (BNC JP18, Din pin of the NT U-Interface Transceiver) to the Transmit
Data Output of the BERT box.
c. Connect NTCLK (BNC J21, gated clock output for the B1+B2+D time slot) to the External
Transmit and External Receive Clock inputs of the BERT box.
2. Verify that the DIP switches are set as in Figure 1-3 (valid for above-mentioned BERT boxes).
3. Congure the bit error rate tester to transmit data on the rising edge of the data clock and receive
data on the falling edge of the data clock.
4. Using an ASCII terminal connected to J16, activate the MC145572EVK using the activation menu
item J. Activate both U chips, 2B+D loop back to U-Interface at LT end, disable S/T chip.
5. Begin bit error rate testing when status LEDs indicate loop is successfully activated.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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