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參數(shù)資料
| 型號： | MC145202-1 |
| 廠商： | Motorola, Inc. |
| 英文描述： | PLL Frequency Synthesizer(2.0GHz PLL頻率合成器) |
| 中文描述： | 鎖相環(huán)頻率合成器（2.0GHz的鎖相環(huán)頻率合成器） |
| 文件頁數(shù)： | 9/23頁 |
| 文件大?。?/td> | 270K |
| 代理商： | MC145202-1 |
MC145202–1
PIN DESCRIPTIONS
9
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS – RF AND IF DEVICE DATA
DIGITAL INTERFACE PINS
Din
Serial Data Input (Pin 19)
The bit stream begins with the most significant bit (MSB)
and is shifted in on the low–to–high transition of CLK. The bit
pattern is 1 byte (8 bits) long to access the C or configuration
register, 2 bytes (16 bits) to access the first buffer of the R
register, or 3 bytes (24 bits) to access the A register (see
Table 4). The values in the C, R, and A registers do not
change during shifting because the transfer of data to the
registers is controlled by ENB.
CAUTION
The value programmed for the N counter must be
greater than or equal to the value of the A counter.
The 13 least significant bits (LSBs) of the R register are
double–buffered. As indicated above, data is latched into the
first buffer on a 16–bit transfer. (The 3 MSBs are not
double–buffered and have an immediate effect after a 16–bit
transfer.) The second buffer of the R register contains the 13
bits for the R counter. This second buffer is loaded with the
contents of the first buffer when the A register is loaded (a
24–bit transfer). This allows presenting new values to the R,
A, and N counters simultaneously. If this is not required, then
the 16–bit transfer may be followed by pulsing ENB low with
no signal on the CLK pin. This is an alternate method of
transferring data to the second buffer of the R register (see
Figure 16).
The bit stream needs neither address nor steering bits due
to the innovative BitGrabber Plus registers. Therefore, all bits
in the stream are available to be data for the three registers.
Random access of any register is provided (i.e., the registers
may be accessed in any sequence). Data is retained in the
registers over a supply range of 2.7 to 5.5 V. The formats are
shown in Figures 14, 15, and 16.
Din typically switches near 50% of VDD to maximize noise
immunity. This input can be directly interfaced to CMOS
devices with outputs guaranteed to switch near rail–to–rail.
When interfacing to NMOS or TTL devices, either a level
shifter (MC74HC14A, MC14504B) or pull–up resistor of 1 k
to 10 k
must be used. Parameters to consider when sizing
the resistor are worst–case IOL of the driving device,
maximum tolerable power consumption, and maximum data
rate.
Table 4. Register Access
(MSBs are shifted in first; C0, R0, and A0 are the LSBs)
Number
of Clocks
Accessed
Register
Bit
Nomenclature
8
16
24
Other Values
≤
32
Values > 32
C Register
R Register
A Register
Not Allowed
See Figures
22 – 25
C7, C6, C5, . . ., C0
R15, R14, R13, . . ., R0
A23, A22, A21, . . ., A0
CLK
Serial Data Clock Input (Pin 18)
Low–to–high transitions on CLK shift bits available at the
Din pin, while high–to–low transitions shift bits from Output A
(when configured as Data Out, see Pin 16). The
24–1/2–stage shift register is static, allowing clock rates
down to dc in a continuous or intermittent mode.
Eight clock cycles are required to access the C register.
Sixteen clock cycles are needed for the first buffer of the R
register. Twenty–four cycles are used to access the A
register. See Table 4 and Figures 14, 15, and 16. The number
of clocks required for cascaded devices is shown in Figures
23 through 25.
CLK typically switches near 50% of VDD and has a
Schmitt–triggered input buffer. Slow CLK rise and fall times
are allowed. See the last paragraph of
Din
for more
information.
NOTE
To guarantee proper operation of the power–on
reset (POR) circuit, the CLK pin must be held at
Gnd (with ENB being a don’t care) or ENB must
be held at the potential of the V+ pin (with CLK
being a don’t care) during power–up. Floating,
toggling, or having these pins in the wrong state
during power–up does not harm the chip, but
causes two potentially undesirable effects. First,
the outputs of the device power up in an unknown
state. Second, if two devices are cascaded, the A
Registers must be written twice after power up.
After these two accesses, the two cascaded chips
perform normally.
ENB
Active Low Enable Input (Pin 17)
This pin is used to activate the serial interface to allow the
transfer of data to/from the device. When ENB is in an
inactive high state, shifting is inhibited and the port is held in
the initialized state. To transfer data to the device, ENB
(which must start inactive high) is taken low, a serial transfer
is made via Din and CLK, and ENB is taken back high. The
low–to–high transition on ENB transfers data to the C or A
registers and first buffer of the R register, depending on the
data stream length per Table 4.
Transitions on ENB must not be attempted while CLK is
high. This puts the device out of synchronization with the
microcontroller. Resynchronization occurs when ENB is high
and CLK is low.
This input is also Schmitt–triggered and switches near
50% of VDD, thereby minimizing the chance of loading
erroneous data into the registers. See the last paragraph of
Din
for more information.
For POR information, see the note for the
CLK pin
.
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