參數(shù)資料
型號: MC145202-1
廠商: Motorola, Inc.
英文描述: PLL Frequency Synthesizer(2.0GHz PLL頻率合成器)
中文描述: 鎖相環(huán)頻率合成器(2.0GHz的鎖相環(huán)頻率合成器)
文件頁數(shù): 20/23頁
文件大?。?/td> 270K
代理商: MC145202-1
MC145202–1
20
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS – RF AND IF DEVICE DATA
Threshold
Detector
Low–pass
Filter
NC
1000 pF
UHF
VCO
Integrator
MCU
+3 V
General–purpose
Digital Output
+3 V
REFout
REFin
VCC
VDD
Gnd
LD
φ
R
φ
V
VPD
PDout
Rx
Test 1
fin
fin
Test 2
Output B
Output A
ENB
CLK
Din
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Q1
NC
+ 3 V
UHF Output
Buffer
Note 2
NOTES:
1
When used, the
φ
R and
φ
V outputs are fed to an external combiner/loop filter. See the Phase–
Locked Loop — Low–Pass Filter Design (Page 19) for additional information.
Transistor Q1 is required only if the standby feature is needed. Q1 permits the bipolar section
of the device to be shut down via use of the general–purpose digital pin, Output B. If the standby
feature is not needed, tie Pin 12 directly to the power supply.
For optimum performance, bypass the VCC, VDD, and VPD pins to Gnd with low–inductance ca-
pacitors.
The R counter is programmed for a divide value = REFin/fR. Typically, fR is the tuning resolution
required for the VCO. Also, the VCO frequency divided by fR = NT = N x 64 + A; this determines
the values (N, A) that must be programmed into the N and A counters, respectively.
2
3
4
Figure 21. Example Application
CMOS
MCU
Output A
(Data Out)
ENB
CLK
Din
Device #1
(MC145193 or MC145202–1)
Output A
(Data Out)
ENB
CLK
Din
Device #2
(MC145193 or MC145202–1)
Optional
NOTE: See related Figures 23, 24, and 25.
Figure 22. Cascading Two Devices
相關(guān)PDF資料
PDF描述
MC145225 Dual PLL Frequency Synthesizers With DACs and Voltage Multipliers(帶DACs和電壓乘法器的雙PLL頻率合成器)
MC145230 Dual PLL Frequency Synthesizers With DACs and Voltage Multipliers(帶DACs和電壓乘法器的雙PLL頻率合成器)
MC14528BCL Dual Monostable Multivibrator
MC14528 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
MC14528 Dual Monostable Multivibrator
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