參數(shù)資料
型號(hào)： MC145202-1
廠商： Motorola, Inc.
英文描述： PLL Frequency Synthesizer(2.0GHz PLL頻率合成器)
中文描述： 鎖相環(huán)頻率合成器（2.0GHz的鎖相環(huán)頻率合成器）
文件頁(yè)數(shù)： 19/23頁(yè)
文件大?。?/td> 270K
代理商： MC145202-1
MC145202–1
19
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS – RF AND IF DEVICE DATA
F(s) =
Assumng Gain A is very large, then:
Z(s) =
ζ
=
ω
n =
PHASE–LOCKED LOOP — LOW–PASS FILTER DESIGN
(B)
A
C
R2
C
VCO
(A)
φ
R
φ
V
R1
R1
R2
K
φ
KVCO
NC
R
2
sC
ω
n =
K
φ
KVCO
NCR1
ζ
=
ω
nR2C
2
R2sC + 1
R1sC
NOTE:
For (B), R1 is frequently split into two series resistors; each resistor is equal to R1 divided by 2. A capacitor CC is then placed from the midpoint
to ground to further filter the error pulses. The value of CC should be such that the corner frequency of this network does not significantly
affect
ω
n.
DEFINITIONS:
N = Total Division Ratio in Feedback Loop
K
φ
(Phase Detector Gain) = IPDout/2
π
amps per radian for PDout
K
φ
(Phase Detector Gain) = VPD/2
π
volts per radian for
φ
V and
φ
R
KVCO (VCO Transfer Function) =
2
π
fVCO
VVCO
For a nominal design starting point, the user might consider a damping factor
ζ
≈
0.7 and a natural loop frequency
ω
n
≈
(2
π
fR/50) where fR
is the frequency at the phase detector input. Larger
ω
n values result in faster loop lock times and, for similar sideband filtering, higher fR–related
VCO sidebands.
Either loop filter (A) or (B) is frequently followed by additional sideband filtering to further attenuate fR–related VCO sidebands. This additional
filtering may be active or passive.
RECOMMENDED READING:
Gardner, Floyd M., Phaselock Techniques (second edition).New York, Wiley–Interscience, 1979.
Manassewitsch, Vadim, Frequency Synthesizers: Theory and Design (second edition). New York, Wiley–Interscience, 1980.
Blanchard, Alain, Phase–Locked Loops: Application to Coherent Receiver Design.New York, Wiley–Interscience, 1976.
Egan, William F., Frequency Synthesis by Phase Lock. New York, Wiley–Interscience, 1981.
Rohde, Ulrich L., Digital PLL Frequency Synthesizers Theory and Design. Englewood Cliffs, NJ, Prentice–Hall, 1983.
Berlin, Howard M., Design of Phase–Locked Loop Circuits, with Experiments.Indianapolis, Howard W. Sams and Co., 1978.
Kinley, Harold, The PLL Synthesizer Cookbook.Blue Ridge Summit, PA, Tab Books, 1980.
Seidman, Arthur H., Integrated Circuits Applications Handbook Chapter 17, pp. 538–586. New York, John Wiley & Sons.
Fadrhons, Jan, “Design and Analyze PLLs on a Programmable Calculator,” EDN March 5, 1980.
AN535, Phase–Locked Loop Design Fundamentals, Motorola Semiconductor Products, Inc., 1970.
AR254, Phase–Locked Loop Design Articles, Motorola Semiconductor Products, Inc., Reprinted with permission from Electronic Design,
1987.
AN1253, An Improved PLL Design Method Without
ω
n and
ζ
, Motorola Semiconductor Products, Inc., 1995.
–
+
KVCOC
N
K
φ
1 + sRC
NOTE:
For (A), using K
φ
in amps per radian with the filter’s impedance transfer function, Z(s), maintains units of volts per radian for the detector/filter
combination. Additional sideband filtering can be accomplished by adding a capacitor C
′
across R. The corner
ω
c = 1/RC
′
should be chosen
such that
ω
n is not significantly affected.
C
VCO
R
PDout
radians per volt
=
ω
nRC
2
相關(guān)PDF資料
PDF描述
MC145225 Dual PLL Frequency Synthesizers With DACs and Voltage Multipliers(帶DACs和電壓乘法器的雙PLL頻率合成器)
MC145230 Dual PLL Frequency Synthesizers With DACs and Voltage Multipliers(帶DACs和電壓乘法器的雙PLL頻率合成器)
MC14528BCL Dual Monostable Multivibrator
MC14528 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
MC14528 Dual Monostable Multivibrator
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC14520B 制造商:Motorola Inc 功能描述: 制造商:ON Semiconductor 功能描述:
MC14520BAL 制造商:Motorola Inc 功能描述:Counter, Up, 4 Bit Binary, 16 Pin, Ceramic, DIP
MC14520BCP 功能描述:計(jì)數(shù)器移位寄存器 3-18V Dual BCD Up RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel
MC14520BCPG 功能描述:計(jì)數(shù)器移位寄存器 3-18V Dual BCD Up RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel
MC14520BDW 功能描述:計(jì)數(shù)器移位寄存器 3-18V Dual BCD Up RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*